Datasheet

R01DS0098EJ0180 Rev.1.80 Page 171 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
Figure 5.34 I/O Port Input Timing
Figure 5.35 MTU Input/Output Timing
Table 5.26 Timing of On-Chip Peripheral Modules (8)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.7V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0V, PIXCLK = 27MHz, T
a
= T
opr
Item Symbol min typ max Unit Test Conditions
PDC VSYNC/HSYNC input setup time t
SYNCSETUP
10 — — ns Figure 5.58
VSYNC/HSYNC input hold time t
SYNCHOLD
5 ——ns
PIXD input setup time t
DATASETUP
10——ns
PIXD input hold time t
DATAHOLD
5 ——ns
PIXCLK input cycle time t
PIXcyc
37 — 1000 ns Figure 5.59
PIXCLK input pulse width high level t
PIXH
10——ns
PIXCLK input pulse width low level t
PIXL
10——ns
PCKO pin output cycle time t
PCKcyc
40 — 1000 ns Figure 5.60
PCKO pin output high level pulse width t
PCKH
13——ns
PCKO pin output low level pulse width t
PCKL
13——ns
PCKO pin output rising time t
PCKr
——5 ns
PCKO pin output falling time t
PCKf
——5 ns
Port
PCLK
t
PRW
Output compare
output
Input capture
input
PCLK
t
TICW