Datasheet

R01DS0098EJ0180 Rev.1.80 Page 170 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0.
Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER
Table 5.25 Timing of On-Chip Peripheral Modules (7)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
ICLK = 12.5 to 100 MHz, T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit
Test
Conditions
ETHERC(RMII) REF50CK cycle time T
ck
20 — ns Figure 5.48 to
Figure 5.51
REF50CK frequency
Typ. 50 MHz
— — 50 + 100ppm MHz
REF50CK duty — 35 65 %
REF50CK rise/fall time T
ckr/ckf
0.5 3.5 ns
RMII_xxxx*
1
output delay time T
co
2.5 15.0 ns
RMII_xxxx*
2
setup time T
su
3— ns
RMII_xxxx*
2
hold time T
hd
1— ns
RMII_xxxx*
1,
*
2
rise/fall time Tr/Tf 0.5 6 ns
ET_WOL output delay time t
WOLd
1 23.5 ns Figure 5.52
ETHERC(MII) ET_TX_CLK cycle time t
Tcy c
40 — ns —
ET_TX_EN output delay time t
TENd
1 20 ns Figure 5.53
ET_ETXD0 to ET_ETXD3 output delay time t
MTDd
120 ns
ET_CRS setup time t
CRSs
10 — ns
ET_CRS hold time t
CRSh
10 — ns
ET_COL setup time t
COLs
10 — ns Figure 5.54
ET_COL hold time t
COLh
10 — ns
ET_RX_CLK cycle time t
TRcyc
40 — ns —
ET_RX_DV setup time t
RDVs
10 ns Figure 5.55
ET_RX_DV hold time t
RDVh
10 — ns
ET_ERXD0 to ET_ERXD3 setup time t
MRDs
10 — ns
ET_ERXD0 to ET_ERXD3 hold time t
MRDh
10 — ns
ET_RX_ER setup time t
RERs
10 — ns Figure 5.56
ET_RX_ER hold time t
RESh
10 — ns
ET_WOL output delay time t
WOLd
1 23.5 ns Figure 5.57