Datasheet

R01DS0098EJ0180 Rev.1.80 Page 166 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t
Pcyc
: PCLK cycle
Table 5.21 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*
1
, VREFH0 = 2.7 V to AVCC0*
1
,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit*
2
Test Conditions
RSPI Data output delay
time
Master Packages
with 177 to
144 pins
t
OD
— 18 ns Figure 5.43 to
Figure 5.46
C = 30
P
F
Packages
with 100 pins
or less
—30
Slave Packages
with 177 to
144 pins
—3 × t
Pcyc
+ 40
Packages
with 100 pins
or less
—3 × t
Pcyc
+ 50
Data output hold
time
Master t
OH
0—ns
Slave 0 —
Successive
transmission delay
time
Master t
TD
t
SPcyc
+ 2 × t
Pcyc
8 × t
SPcyc
+ 2 × t
Pcyc
ns
Slave 4 × t
Pcyc
—
MOSI and MISO
rise/fall time
Output Packages
with 177 to
144 pins
t
Dr,
t
Df
—5ns
Packages
with 100 pins
or less
—10
Input — 1 μs
SSL rise/fall time Output Packages
with 177 to
144 pins
t
SSLr,
t
SSLf
—5ns
Packages
with 100 pins
or less
—10
Input — 1 μs
Slave access time t
SA
—4t
Pcyc
Figure 5.45 and
Figure 5.46
C = 30
P
F
Slave output release time t
REL
—3t
Pcyc