Datasheet

R01DS0098EJ0180 Rev.1.80 Page 165 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t
Pcyc
: PCLK cycle
Table 5.20 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*
1
, VREFH0 = 2.7 V to AVCC0*
1
,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit*
2
Test Conditions
RSPI RSPCK clock cycle Master t
SPcyc
2 4096 t
Pcyc
Figure 5.42
C = 30
P
F
Slave 8 4096
RSPCK clock high
pulse width
Master t
SPCKWH
(t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2 – 3
—ns
Slave (t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2
—
RSPCK clock low
pulse width
Master t
SPCKWL
(t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2 – 3
—ns
Slave (t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2
—
RSPCK clock rise/
fall time
Output [packages with 177 to
144 pins]
t
SPCKr,
t
SPCKf
—5ns
Output [packages with 100
pins or less]
—10
Input — 1 μs
Data input setup time Master
[packages
with 177 to
144 pins]
VCC
 3.0 V t
SU
15 — ns Figure 5.43 to
Figure 5.46
C = 30
P
F
VCC < 3.0 V 20 —
Master [packages with 100
pins or less]
30 —
Slave 20
– t
Pcyc
—
Data input hold time Master t
H
0—ns
Slave 20 + 2 × t
Pcyc
—
SSL setup time Master t
LEAD
18t
SPcyc
Slave 4 — t
Pcyc
SSL hold time Master t
LAG
18t
SPcyc
Slave 4 — t
Pcyc