Datasheet

R01DS0098EJ0180 Rev.1.80 Page 164 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3.7 Timing of On-Chip Peripheral Modules
Note 1. t
Pcyc
: PCLK cycle
Table 5.19 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit*
1
Test
Conditions
I/O ports Input data pulse width t
PRW
1.5 — t
Pcyc
Figure 5.34
MTU/TPU Input capture input pulse
width
Single-edge
setting
t
TICW
1.5 — t
Pcyc
Figure 5.35
Both-edge
setting
2.5 —
Timer clock pulse width Single-edge
setting
t
TCKWH,
t
TCKWL
1.5 — t
Pcyc
Figure 5.36
Both-edge
setting
2.5 —
Phase counting
mode
2.5 —
POE POE# input pulse width t
POEW
1.5 — t
Pcyc
Figure 5.37
8-bit timer Timer clock pulse width Single-edge
setting
t
TMCWH,
t
TMCWL
1.5 — t
Pcyc
Figure 5.38
Both-edge
setting
2.5 —
SCI Input clock cycle Asynchronous t
Scyc
4—t
Pcyc
Figure 5.39
Clock
synchronous
6—
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
—20ns
Input clock fall time t
SCKf
—20ns
Output clock cycle Asynchronous t
Scyc
16 — t
Pcyc
Clock
synchronous
4—
Output clock pulse width t
SCKW
0.4 0.6 t
Scyc
Output clock rise time t
SCKr
—20ns
Output clock fall time t
SCKf
—20ns
Transmit data delay time Clock
synchronous
t
TXD
— 40 ns Figure 5.40
Receive data setup time Clock
synchronous
t
RXS
40 — ns
Receive data hold time Clock
synchronous
t
RXH
40 — ns
A/D
converter
10-bit A/D converter trigger input pulse width t
TRGW
1.5 — t
Pcyc
Figure 5.41
12-bit A/D converter trigger input pulse width 1.5 —