Datasheet

R01DS0098EJ0180 Rev.1.80 Page 163 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3.6 EXDMAC Timing
Figure 5.31 EDREQ0 and EDREQ1 Input Timing
Figure 5.32 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
Figure 5.33 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
Table 5.18 EXDMAC Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz, BCLK pin = 8 to 100 MHz, SDCLK pin = 8 to 50 MHz, T
a
= T
opr
High drive output is selected by the drive capacity control register
Item Symbol Min. Max. Unit
Test
Conditions
EXDMAC EDREQ setup time t
EDRQS
20 — ns Figure 5.31
EDREQ hold time t
EDRQH
5 — ns Figure 5.32
and
Figure 5.33
EDACK delay time t
EDACD
—15ns
BCLK pin
t
EDRQS
t
EDRQH
EDREQ0
EDREQ1
EDACK0
EDACK1
t
EDACD
BCLK pin
t
EDACD
t
EDACD
BCLK pin
t
EDACD
EDACK0
EDACK1