Datasheet

R01DS0098EJ0180 Rev.1.80 Page 149 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3.5 Bus Timing
Table 5.16 Bus Timing (packages with 177 to 144 pins)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 100 MHz, BCLK pin = 8 to 50 MHz, SDCLK pin = 8 to 50MHz, T
a
= T
opr
Output load conditions: V
OH
= VCC × 0.5, V
OL
= VCC × 0.5, I
OH
= -1.0 mA, I
OL
= 1.0 mA, C = 30 pF
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
— 15 ns Figure 5.17 to
Figure 5.22
Byte control delay time t
BCD
—15ns
CS# delay time t
CSD
—15ns
ALE delay time t
ALED
—20ns
RD# delay time t
RSD
—15ns
Read data setup time t
RDS
15 — ns
Read data hold time t
RDH
0—ns
WR# delay time t
WRD
—15ns
Write data delay time t
WDD
—15ns
Write data hold time t
WDH
0—ns
WAIT# setup time t
WTS
15 — ns Figure 5.23
WAIT# hold time t
WTH
0—ns
Address delay time 2 (SDRAM) t
AD2
1 15 ns Figure 5.24 to
Figure 5.30
CS# delay time 2 (SDRAM) t
CSD2
115ns
DQM delay time (SDRAM) t
DQMD
115ns
CKE delay time (SDRAM) t
CKED
115ns
Read data setup time 2 (SDRAM) t
RDS2
12 — ns
Read data hold time 2 (SDRAM) t
RDH2
0—ns
Write data delay time 2 (SDRAM) t
WDD2
—15ns
Write data hold time 2 (SDRAM) t
WDH2
1—ns
WE# delay time (SDRAM) t
WED
115ns
RAS# delay time (SDRAM) t
RASD
115ns
CAS# delay time (SDRAM) t
CASD
115ns