Datasheet

R01DS0098EJ0180 Rev.1.80 Page 143 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles n selected by the value of the SOSCWTCR.SSTS[4:0] bits determines the sub-clock oscillation
stabilization waiting time in accord with the formula below.
The notation “max (t
SUBOSC
, t
SUBOSCWT0
)“ indicates whichever is higher of t
SUBOSC
and t
SUBOSCWT0
.
Note 3. The minimum value and maximum value of the sub-clock oscillation stabilization wait offset time (tSUBOSCWT0) is the
references only for 100-pin or more products. For 64-pin products, consider the value of tSUBOSCWT0 to be 0.
Figure 5.3 BCLK Pin Output, SDCLK Pin Output Timing
Figure 5.4 EXTAL External Clock Input Timing
Table 5.13 Clock Timing (Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, V
BATT
= 2.0 to 3.6 V (for products
with 100 pins or more), V
BATT
= 2.3 to 3.6 V (for the 64-pin product),
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Sub-clock frequency f
SUB
— 32.768 — kHz
Sub-clock oscillator start-up time t
SUBOSC
—— *
1
Figure 5.12
Sub-clock oscillation stabilization wait offset time*
3
t
SUBOSCWT0
1.8 — 2.6 s
Sub-clock oscillation stabilization wait time t
SUBOSCWT
—— *
2
s
t
SUBOSCWT
n
f
SUB
max (t
SUBOSC,
t
SUBOSCWT0
)
=
+
t
Cf
t
CH
t
Bcyc
, t
SDcyc
t
Cr
t
CL
BCLK pin output, SDCLK pin output
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
t
EXH
t
EXcyc
EXTAL external clock input
VCC × 0.5
t
EXL
t
EXr
t
EXf