Datasheet
R01DS0098EJ0180 Rev.1.80 Page 141 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3.2 Clock Timing
Table 5.12 Clock Timing (Except for Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Test
Conditions
BCLK pin output cycle time
Packages with 177 to 144
pins
t
Bcyc
20 — —
ns
Figure 5.3
Packages with 100 pins or
less
40 — —
ns
BCLK pin output high pulse width t
CH
5——ns
BCLK pin output low pulse width t
CL
5——ns
BCLK pin output rising time t
Cr
——5 ns
BCLK pin output falling time t
Cf
——5 ns
SDCLK pin output cycle time only 177 to 144 pin t
Bcyc
20 — — ns
SDCLK pin output high pulse width t
CH
5——ns
SDCLK pin output low pulse width t
CH
5——ns
SDCLK pin output rising time t
CH
——5 ns
SDCLK pin output falling time t
CH
——5 ns
EXTAL external clock input cycle time t
EXcyc
50 — — ns Figure 5.4
EXTAL external clock input high pulse width t
EXH
20 — — ns
EXTAL external clock input low pulse width t
EXL
20 — — ns
EXTAL external clock rising time t
EXr
——5 ns
EXTAL external clock falling time t
EXf
——5 ns
EXTAL external clock input wait time*
1
t
EXWT
1——ms
Main clock frequency f
MAIN
4 — 16 MHz
Main clock oscillator start-up time t
MAINOSC
———*
3
ms Figure 5.5
Main clock oscillation stabilization wait time t
MAINOSCWT
———*
4
ms
LOCO and IWDTCLK clock cycle time t
cyc
6.96 8 9.4 µs
LOCO and IWDTCLK clock oscillation frequency f
LOCO
106.25 125 143.75 kHz
LOCO and IWDTCLK clock oscillation stabilization wait time t
LOCOWT
— — 20 µs Figure 5.6
HOCO clock oscillator oscillation frequency f
HOCO
45 50 55 MHz
HOCO clock oscillation stabilization wait time 1*
2
t
HOCOWT1
— — 1.8 ms Figure 5.7
HOCO clock oscillation stabilization wait time 2 t
HOCOWT2
— — 2.0 ms Figure 5.8
HOCO clock power supply settling time t
HOCOP
— — 1 ms Figure 5.9
PLL clock frequency f
PLL
104 — 200 MHz
PLL lock time PLL operation started
after main clock
oscillation has settled
t
PLL1
— — 500 µs Figure 5.10
PLL clock oscillation stabilization
wait time
t
PLLWT1
———*
5
ms
PLL lock time
PLL operation started
before main clock
oscillation has settled
t
PLL2
——
t
MAINOSC
+t
PLL1
ms
Figure 5.11
PLL clock oscillation stabilization
wait time
t
PLLWT2
———*
5
ms