Datasheet

R01DS0098EJ0180 Rev.1.80 Page 139 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3.1 Reset Timing
Table 5.10 Operation Frequency Value (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Operation
frequency
System clock (ICLK) f 32 — 143.75 kHz
Peripheral module clock (PCLKA) — — 143.75
Peripheral module clock (PCLKB) — — 143.75
FlashIF clock (FCLK) 32 — 143.75
External bus clock (BCLK) Packages with 177 to 144 pins — — 143.75
Packages with 100 pins or less — — 143.75
BCLK pin output Packages with 177 to 144 pins — — 143.75
Packages with 100 pins or less — — 143.75
SDRAM clock (SDCLK) Packages with 177 to 144 pins
only
— — 143.75
SDCLK pin output Packages with 177 to 144 pins
only
— — 143.75
USB clock (UCLK) — — 143.75
IEBUS clock (IECLK) — — 143.75
Table 5.11 Reset Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Test
Conditions
RES# pulse
width
Power-on t
RESWP
2 — — ms Figure 5.1
Deep software standby mode t
RESWD
1 — — ms Figure 5.2
Software standby mode, low-speed
operating mode 2
t
RESWS
1——ms
Programming or erasure of the ROM or E2
data-flash memory or blank checking of the
E2 DataFlash memory
t
RESW
200 — — µs
Other than above t
RESW
200 — — µs
Wait time after RES# cancellation t
RESWT
59 — 60 t
cyc
Figure 5.1
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
t
RESW2
112 — 120 t
cyc