Datasheet

R01DS0098EJ0180 Rev.1.80 Page 138 of 208
May 13, 2014
RX63N Group, RX631 Group 5. Electrical Characteristics
5.3 AC Characteristics
Note 1. The ICLK and PCLKA frequencies must be the same and at least 12.5 MHz if the Ethernet controller is in use
Note 2. The PCLKB must run at a frequency of at least 24 MHz if the USB is in use.
Note 3. The FCLK must run at a frequency of at least 4 MHz when changing the ROM or E2 DataFlash memory contents.
Table 5.8 Operation Frequency Value (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Operation
frequency
System clock (ICLK) f —*
1
—100MHz
Peripheral module clock (PCLKA) —*
1
—100
Peripheral module clock (PCLKB) —*
2
—50
FlashIF clock (FCLK) —*
3
—50
External bus clock (BCLK) Packages with 177 to 144 pins — — 100
Packages with 100 pins or less — — 50
BCLK pin output Packages with 177 to 144 pins — — 50
Packages with 100 pins or less — — 25
SDRAM clock (SDCLK) Packages with 177 to 144 pins
only
——50
SDCLK pin output Packages with 177 to 144 pins
only
——50
USB clock (UCLK) — — 48
IEBUS clock (IECLK) — — 44.03
Table 5.9 Operation Frequency Value (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Operation
frequency
System clock (ICLK) f — — 1 MHz
Peripheral module clock (PCLKA) — — 1
Peripheral module clock (PCLKB) — — 1
FlashIF clock (FCLK) — — 1
External bus clock (BCLK) Packages with 177 to 144 pins — — 1
Packages with 100 pins or less — — 1
BCLK pin output Packages with 177 to 144 pins — — 1
Packages with 100 pins or less — — 1
SDRAM clock (SDCLK) Packages with 177 to 144 pins
only
——1
SDCLK pin output Packages with 177 to 144 pins
only
——1
USB clock (UCLK) — — 1
IEBUS clock (IECLK) — — 1