Datasheet
R01DS0098EJ0180 Rev.1.80 Page 129 of 208
May 13, 2014
RX63N Group, RX631 Group 4. I/O Registers
007F C402h FLASH Flash mode register FMODR 8 8 2 to 4 FCLK 2, 3 ICLK Flash Memory
007F C410h FLASH Flash access status register FASTAT 8 8 2 to 4 FCLK 2, 3 ICLK
007F C411h FLASH Flash access error interrupt enable register FAEINT 8 8 2 to 4 FCLK 2, 3 ICLK
007F C412h FLASH Flash ready interrupt enable register FRDYIE 8 8 2 to 4 FCLK 2, 3 ICLK
007F C440h FLASH E2 DataFlash read enable register 0 DFLRE0 16 16 2 to 4 FCLK 2, 3 ICLK
007F C442h FLASH E2 DataFlash read enable register 1 DFLRE1 16 16 2 to 4 FCLK 2, 3 ICLK
007F C450h FLASH E2 DataFlash P/E enable register 0 DFLWE0 16 16 2 to 4 FCLK 2, 3 ICLK
007F C452h FLASH E2 DataFlash P/E enable register 1 DFLWE1 16 16 2 to 4 FCLK 2, 3 ICLK
007F C454h FLASH FCU RAM enable register FCURAME 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFB0h FLASH Flash status register 0 FSTATR0 8 8 2 to 4 FCLK 2, 3 ICLK
007F FFB1h FLASH Flash status register 1 FSTATR1 8 8 2 to 4 FCLK 2, 3 ICLK
007F FFB2h FLASH Flash P/E mode entry register FENTRYR 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFB4h FLASH Flash protection register FPROTR 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFB6h FLASH Flash reset register FRESETR 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFBAh FLASH FCU command register FCMDR 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFCAh FLASH E2 data flash blank check control register DFLBCCNT 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFCCh FLASH Flash P/E status register FPESTAT 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFCEh FLASH E2 DataFlash blank check status register DFLBCSTAT 16 16 2 to 4 FCLK 2, 3 ICLK
007F FFE8h FLASH Peripheral clock notification register PCKAR 16 16 2 to 4 FCLK 2, 3 ICLK
FEFF FAC0h FLASH Unique ID register 0*
8
UIDR0 8 8 1 ICLK 1 ICLK
FEFF FAC1h FLASH Unique ID register 1*
8
UIDR1 8 8 1 ICLK 1 ICLK
FEFF FAC2h FLASH Unique ID register 2*
8
UIDR2 8 8 1 ICLK 1 ICLK
FEFF FAC3h FLASH Unique ID register 3*
8
UIDR3 8 8 1 ICLK 1 ICLK
FEFF FAC4h FLASH Unique ID register 4*
8
UIDR4 8 8 1 ICLK 1 ICLK
FEFF FAC5h FLASH Unique ID register 5*
8
UIDR5 8 8 1 ICLK 1 ICLK
FEFF FAC6h FLASH Unique ID register 6*
8
UIDR6 8 8 1 ICLK 1 ICLK
FEFF FAC7h FLASH Unique ID register 7*
8
UIDR7 8 8 1 ICLK 1 ICLK
FEFF FAC8h FLASH Unique ID register 8*
8
UIDR8 8 8 1 ICLK 1 ICLK
FEFF FAC9h FLASH Unique ID register 9*
8
UIDR9 8 8 1 ICLK 1 ICLK
FEFF FACAh FLASH Unique ID register 10*
8
UIDR10 8 8 1 ICLK 1 ICLK
FEFF FACBh FLASH Unique ID register 11*
8
UIDR11 8 8 1 ICLK 1 ICLK
FEFF FACCh FLASH Unique ID register 12*
8
UIDR12 8 8 1 ICLK 1 ICLK
FEFF FACDh FLASH Unique ID register 13*
8
UIDR13 8 8 1 ICLK 1 ICLK
FEFF FACEh FLASH Unique ID register 14*
8
UIDR14 8 8 1 ICLK 1 ICLK
FEFF FACFh FLASH Unique ID register 15*
8
UIDR15 8 8 1 ICLK 1 ICLK
FEFF FAD2h TEMPS Temperature sensor calibration data register*
8
TSCDRL 8 8 1 ICLK 1 ICLK Temperature
sensor
FEFF FAD3h TEMPS Temperature sensor calibration data register*
8
TSCDRH 8 8 1 ICLK 1 ICLK
Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively.
Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively.
Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Note 5. Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 27.4 lists
register allocation for 16-bit access in the User’s manual: Hardware.
Note 6. When the register is accessed while the USB is operating, a delay may be generated in accessing.
Note 7. The addresses with odd number cannot be accessed in 16-bit units. 16-bit access to a register should be made to the addresses of the TMOCNTL register. Allocation of
registers to be accessed in 16-bit units is described in the Table 36.6, Allocation of Registers to be Accessed in 16-bit Units in the User’s manual: Hardware.
Note 8. These registers are only present in the G version.
Table 4.1 List of I/O Registers (Address Order) (50/50)
Address
Module
Symbol Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
Related
Function
ICLKPCLK ICLK<PCLK