Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 176 (24x24) 32-Bit 100 MHz I/O number 133

RX63N Group, RX631 Group

Renesas MCUs

R01DS0098EJ0180 Rev.1.80 Page 1 of 208

May 13, 2014

Features

RX63N Group products incorporate an Ethernet controller while

RX631 Group products do not.

■ 32-bit RX CPU core

 Max. operating frequency: 100 MHz

 Capable of 165 DMIPS in operation at 100 MHz

 Single precision 32-bit IEEE-754 floating point

 Two types of multiply-and-accumulation unit (between memories and

between registers)

 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 JTAG and FINE (two-line) debugging interfaces

■ Low-power design and architecture

 Operation from a single 2.7- to 3.6-V supply

 Low power consumption: A product that supports all peripheral functions

draws only 500 μA/MHz.

 RTC is capable of operation from a dedicated power supply (min. operating

voltage: 2.3 V).

 Four low-power modes

■ On-chip main flash memory, no wait states

 Supports ROM-less versions and versions with up to 2 Mbytes of ROM

(ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only)

 100-MHz operation, 10-ns read cycle (no wait states)

 768-Kbyte to 2-Mbyte capacities

 User code is programmable by on-board or off-board programming

■ On-chip data flash memory

 ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM, no wait states

 64 Kbytes/128 Kbytes/192 Kbytes/256 Kbytes of SRAM

 For instructions and operands

 Can provide backup on deep software standby

■ DMA

 DMAC: Four channels

 DTC

 EXDMAC: Two channels

 Dedicated DMAC for the Ethernet controller: Single channel

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 External crystal oscillator or internal PLL for operation at 4 to 16 MHz

 Internal 125-kHz LOCO and 50-MHz HOCO

 125-kHz clocks for the IWDT

■ Real-time clock

 Adjustment functions (30 seconds, leap year, and error)

 Time capture function

(for capturing times in response to event-signal input on external pins)

■ Independent watchdog timer

 125-kHz LOCO clock operation

■ Useful functions for IEC60730 compliance

 Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-

diagnostic function for the A/D converter, etc.

■ Various communications interfaces

 Ethernet MAC (1) (not in RX631 Group products)

 Host/function or OTG controller (1) and function controller (1) with full-

speed USB 2.0 transfer

 CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3

modules)

 SCI with multiple functionalities (up to 13)

 Choose from among asynchronous mode, clock-synchronous mode, smart-

card interface mode, simplified SPI, simplified I2C, and extended serial

mode.

C bus interface for transfer at up to 1 Mbps (up to 4)

 RSPI for high-speed transfer (up to 3)

 Parallel data capture unit (PDC) (1) (available for 512 Kbytes/384 Kbytes/

256 Kbytes flash memory with 177-pin, 176-pin, 145-pin, and 144-pin)

■ External address space

 Buses for high-speed data transfer (max. operating frequency of 50 MHz)

 8 CS areas (8 × 16 Mbytes)

 Multiplexed bus or separate bus are selectable per area.

 8-, 16-, or 32-bit bus space is selectable per area

 Independent SDRAM area (128 Mbytes)

■ Up to 20 extended-function timers

 16-bit MTU2: input capture, output compare, PWM waveform output,

phase-counting mode (6 channels)

 16-bit TPU: input capture, output compare, phase-counting mode (12

channels)

 8-bit TMR (4 channels)

 16-bit compare-match timers (4 channels)

■ A/D converter for 1-MHz Operation

 Up to 21 × 12-bit channels, and incorporating 1 sample-and-hold circuit

Up to 8 × 10-bit channels, and incorporating 1 sample-and-hold circuit

 Addition of results of A/D conversion (in the 12-bit converter)

 Self diagnosis (for the 10-bit converter)

■ 10-bit D/A converter: 2 channels

■ Temperature sensor for measuring temperature within

the chip

■DEU

 AES encryption and decryption functions

 128/192/256-bit key length

 ECB/CBC mode

■ Register write protection can protect values in

important registers against overwriting.

■ Up to 134 pins for general I/O ports

 5-V tolerance, open drain, input pull-up, switchable driving ability

■ Unique ID

 16-byte ID code is provided for each chip (only for the G version)

■ Operating temp. range

 D version: -40 to +85°C

 G version: -40 to +105°C

PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch

PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch

PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch

PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch

PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch

PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch

PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch

PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch

PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch

PLBG0176GA-A 13 × 13mm, 0.8-mm pitch

100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash

memory, various communications interfaces including Ethernet MAC,

full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D

converters, RTC

R01DS0098EJ0180

Rev.1.80

May 13, 2014

Features

Summary of content (210 pages)

PAGE 1
Features RX63N Group, RX631 Group Renesas MCUs R01DS0098EJ0180 Rev.1.80 May 13, 2014 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various communications interfaces including Ethernet MAC, full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D converters, RTC Features RX63N Group products incorporate an Ethernet controller while RX631 Group products do not.
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RX63N Group, RX631 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages in the RX63N/RX631 Group. Table 1.
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RX63N Group, RX631 Group Table 1.1 1.
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RX63N Group, RX631 Group Table 1.1 1.
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RX63N Group, RX631 Group Table 1.1 1.
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RX63N Group, RX631 Group Table 1.1 1. Overview Outline of Specifications (5/6) Classification Module/Function Description Communication function Ethernet controller (ETHERC)     Input and output of Ethernet/IEEE 802.3 frames Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.
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RX63N Group, RX631 Group Table 1.1 1. Overview Outline of Specifications (6/6) Classification Module/Function Description Communication function Parallel data capture unit (PDC)  1 channel  Communicates with an image sensor or other external I/Os and transfer parallel data such as an image output from those devices to internal RAM or external address spaces (CS space and SDRAM space) through DTC or DMAC.
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RX63N Group, RX631 Group Table 1.2 1. Overview Comparison of Functions for Different Packages in the RX63N/RX631 Group Functions RX63N Group 177-pin 176-pin Package External bus width External bus width DMA DMA controller SDRAM area controller 32 bits 145-pin 144-pin 32 bits Not available 100-pin Ch. 0 to 3 Ch. 0 and 1 Not available Available Ch. 0 to 5 Ch. 0 to 11 Ch. 0 to 5 Ch. 0 to 5 Ch. 0 to 5 Port output enable 2 Available Available Ch. 0 and 1 Ch. 0 and 1 8-bit timers Ch.
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RX63N Group, RX631 Group 1.2 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no. Table 1.3 List of Products (1/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (2/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp. Range RX63N (D version) R5F563NDDDLK PTLG0145KA-A 1.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (3/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (4/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp. Range RX631 (D version) R5F5631DCDLC PTLG0177KA-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz -40 to +85°C R5F5631DDDLC PTLG0177KA-A 1.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (5/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (6/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (7/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX63N Group, RX631 Group Table 1.3 1. Overview List of Products (8/8) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp. Range RX631 (G version) *2 R5F5631GDGFB PLQP0144KA-A 1.5 Mbytes 192 Kbytes 32 Kbytes 100 MHz -40 to +105°C R5F5631DDGFB PLQP0144KA-A 1.
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RX63N Group, RX631 Group R 5 F 5 6 3 N A C D 1. Overview F P Package type, number of pins, and pin pitch FC : LQFP/176/0.50 BG: LFBGA/176/0.80 LC : TFLGA/177/0.50 FB : LQFP/144/0.50 LK : TFLGA/145/0.50 LJ : TFLGA/100/0.65 FP : LQFP/100/0.50 LH: TFLGA/64/0.65 FM: LQFP/64/0.50 FL: LQFP/48/0.
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RX63N Group, RX631 Group 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram. DEU E2 Data Flash WDTA IWDTa CRC SCIc × 12 ch SCId × 1 ch USB 2.0 host/function module USB 2.0 function module RSPI (unit 0) PDC ETHERC Internal peripheral buses 1 to 6 RSPI (unit 1) RSPI (unit 2) CAN × 3 ch POE2a TPUa × 6 ch (unit 0) Internal main bus 1 MPU Clock generati on circuit ETHERC EDMAC ICUb DTCa DMACA EXDMACa BSC WDTA IWDTa CRC SCIc, SCId MPU Figure 1.
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RX63N Group, RX631 Group 1.4 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/6) Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-µF capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to VSS via a 0.1-F capacitor. The capacitor should be placed close to the pin. VSS Input Ground pin.
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RX63N Group, RX631 Group Table 1.4 1. Overview Pin Functions (2/6) Classifications Pin Name I/O Description Bus control RD# Output Strobe signal which indicates that reading from the external bus interface space is in progress. WR# Output Strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode.
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RX63N Group, RX631 Group Table 1.4 1. Overview Pin Functions (3/6) Classifications Pin Name I/O Description 16-bit timer pulse unit TIOCA0, TIOCB0 TIOCC0, TIOCD0 I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM output pins. TIOCA1, TIOCB1 I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM output pins. TIOCA2, TIOCB2 I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM output pins.
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RX63N Group, RX631 Group Table 1.4 1. Overview Pin Functions (4/6) Classifications Pin Name Serial communications interface (SCId)  Asynchronous mode/clock synchronous mode I/O Description SCK12 I/O Input/output pin for clock signals. RXD12 Input Input pin for data reception. TXD12 Output Output pin for data transmission.
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RX63N Group, RX631 Group Table 1.4 1. Overview Pin Functions (5/6) Classifications Pin Name I/O Description Ethernet controller ET_MDIO I/O Inputs or outputs bidirectional signals for exchange of management information between the RX63N Group and the PHY-LSI. Parallel data capture unit (PDC) PIXCLK Input Parallel data transfer clock VSYNC Input Vertical synchronization signal HSYNC Input Horizontal synchronization signal PIXD7 to PIXD0 Input 8-bit data USB power pins USB 2.
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RX63N Group, RX631 Group Table 1.4 1. Overview Pin Functions (6/6) Classifications Pin Name I/O Description Analog power supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter. Connect this pin to VCC if the 12-bit A/D converter is not to be used. AVSS0 Input Analog ground pin for the 12-bit A/D converter. Connect this pin to VSS if the 12-bit A/D converter is not to be used. VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter.
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RX63N Group, RX631 Group 1.5 1. Overview Pin Assignments Figure 1.5 to Figure 1.12 show the pins assignments. Table 1.5 to Table 1.13 show the list of pins and pin functions. Power pins and I/O ports are shown in the pin assignment diagrams.
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RX63N Group, RX631 Group 1.
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1.
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RX63N Group, RX631 Group 1.
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73 74 VSS PC0 VCC PC1 75 76 77 PB6 PB7 P73 79 78 PB4 PB5 80 81 82 83 84 85 86 87 88 89 90 PA4 VCC PA5 PA6 PA7 PB0 P71 P72 PB1 PB2 PB3 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 PE3 PE4 PE5 VSS P70 VCC PE6 PE7 P65 P66 P67 PA0 PA1 PA2 PA3 VSS 1.
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RX63N Group, RX631 Group 1.
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Note: Figure 1.9 PE3 PE4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 VCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1.
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RX63N Group, RX631 Group 1. Overview RX631 Group PTLG0064JA-A (64-pin TFLGA) (Top perspective view) Figure 1.
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PB0 VCC PB1 PB3 PB5 PB6 PB7 37 36 35 34 33 VSS 40 38 PA6 41 39 PA3 PA4 43 42 PA0 PA1 PE5 44 PE4 46 45 PE3 47 PE2 49 32 PC2 PE1 50 31 PC3 PE0 51 30 PC4 VREFL 52 29 PC5 P46 53 28 PC6 VREFH 54 27 PC7 P44 55 26 P54 P43 56 25 P42 57 24 P55 VSS_USB P41 58 23 USB0_DP VREFL0 59 22 USB0_DM P40 60 21 VCC_USB VREFH0 61 20 P14 AVCC0 62 19 P15 P05 63 18 P16 AVSS0 64 17 P17 Note: Figure 1.11 1.
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PB1 PB3 PB5 26 25 VCC 28 27 PB0 29 PA4 32 PA6 PA3 33 VSS PA1 30 PE4 34 31 PE3 35 PE2 37 24 PC4 PE1 38 23 PC5 VREFL 39 22 PC6 P46 40 21 VREFH 41 20 PC7 VSS_USB P42 42 19 USB0_DP 18 USB0_DM 17 VCC_USB 16 P14 RX631 Group PLQP0048KB-A (48-pin LQFP) (Top view) 7 8 9 10 11 12 P35/NMI P31 P30 P27 P26 P17 VCC 13 6 48 P36/EXTAL P16 AVSS0 5 14 4 47 VSS P15 AVCC0 P37/XTAL 15 3 VREFH0 46 RES# 45 2 P40 MD/FINED 44 1 VREFL0 VCL P41 4
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RX63N Group, RX631 Group Table 1.5 1.
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RX63N Group, RX631 Group Table 1.5 1.
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RX63N Group, RX631 Group Table 1.5 1.
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RX63N Group, RX631 Group Table 1.5 1.
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RX63N Group, RX631 Group Table 1.5 1.
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RX63N Group, RX631 Group 1. Overview Note 3. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group Table 1.6 1.
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RX63N Group, RX631 Group Table 1.6 1.
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RX63N Group, RX631 Group Table 1.6 1.
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RX63N Group, RX631 Group Table 1.6 1.
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RX63N Group, RX631 Group Table 1.6 1.
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RX63N Group, RX631 Group Table 1.7 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (1/5) Pin No.
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RX63N Group, RX631 Group Table 1.7 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (2/5) Pin No.
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RX63N Group, RX631 Group Table 1.7 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (3/5) Pin No.
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RX63N Group, RX631 Group Table 1.7 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (4/5) Pin No.
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RX63N Group, RX631 Group Table 1.7 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (5/5) Pin No.
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RX63N Group, RX631 Group Table 1.8 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (1/5) Pin No.
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RX63N Group, RX631 Group Table 1.8 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (2/5) Pin No.
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RX63N Group, RX631 Group Table 1.8 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (3/5) Pin No.
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RX63N Group, RX631 Group Table 1.8 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (4/5) Pin No.
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RX63N Group, RX631 Group Table 1.8 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (5/5) Pin No.
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RX63N Group, RX631 Group Table 1.9 Pin No. 100-pin TFLGA List of Pins and Pin Functions (100-Pin TFLGA) (1/5) Power Supply Clock System Control A1 A2 I/O Port Bus EXDMAC Timers Communications (MTU, TPU, TMR, PPG, RTC, POE) (ETHERC, SCIc, SCId, RSPI, RIIC, CAN, IEB, USB) Interrupt S12AD AD DA P05 IRQ13 DA1 P07 IRQ15 ADTRG0# IRQ11-DS AN003 IRQ0 AN008 IRQ4 AN012 VREFH A3 A4 1.
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RX63N Group, RX631 Group Table 1.9 Pin No. 100-pin TFLGA 1.
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RX63N Group, RX631 Group Table 1.9 Pin No. 100-pin TFLGA 1.
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RX63N Group, RX631 Group Table 1.9 Pin No. 100-pin TFLGA 1.
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RX63N Group, RX631 Group Table 1.9 Pin No. 100-pin TFLGA 1.
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RX63N Group, RX631 Group Table 1.10 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (1/4) Pin No.
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RX63N Group, RX631 Group Table 1.10 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (2/4) Pin No.
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RX63N Group, RX631 Group Table 1.10 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (3/4) Pin No.
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RX63N Group, RX631 Group Table 1.10 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (4/4) Pin No. 100-pin LQFP 94 Power Supply Clock System Control 96 VREFH0 97 AVCC0 98 100 Communications (MTU, TPU, TMR, PPG, RTC, POE) (ETHERC, SCIc, SCId, RSPI, RIIC, CAN, IEB, USB) Interrupt S12AD AD DA P40 IRQ8-DS AN000 P07 IRQ15 ADTRG0# P05 IRQ13 DA1 I/O Port Bus EXDMAC VREFL0 95 99 Timers AVSS0 Note 1. Enabled only for the ROM capacity of 768 Kbytes or more Note 2.
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RX63N Group, RX631 Group Table 1.11 Pin No. 64-pin TFLGA 1.
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RX63N Group, RX631 Group Table 1.11 Pin No.
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RX63N Group, RX631 Group Table 1.12 Pin Number 64-Pin LQFP List of Pins and Pin Functions (64-Pin LQFP) (1/3) Power Supply Clock System Control 1 EMLE 2 VCL 3 MD/FINED 4 XCIN 5 XCOUT 6 RES# 7 XTAL 8 VSS 9 EXTAL 10 VCC 11 12 1.
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RX63N Group, RX631 Group Table 1.12 Pin Number 64-Pin LQFP 1.
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RX63N Group, RX631 Group Table 1.12 Pin Number 64-Pin LQFP List of Pins and Pin Functions (64-Pin LQFP) (3/3) Power Supply Clock System Control 61 VREFH0 62 AVCC0 63 64 1. Overview I/O Port P05 Timer Timer Communications (MTU2a, TPUa, TMR, PPG, RTCa, POE2a) (SCIc, SCId, RSPI, RIIC, CAN, IEB, USB) Interrupt S12ADa, DAa IRQ13 DA1 AVSS0 R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group Table 1.13 Pin Number 48-Pin LQFP 1 1.
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RX63N Group, RX631 Group Table 1.13 Pin Number 1.
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RX63N Group, RX631 Group 2. 2. CPU CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions.
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RX63N Group, RX631 Group 2.1 2. CPU General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.
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RX63N Group, RX631 Group 2.3 (1) 2. CPU Register Associated with DSP Instructions Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator.
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RX63N Group, RX631 Group 3. Address Space 3.1 Address Space 3. Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the operating mode and states of control bits. R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 3.
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RX63N Group, RX631 Group 3.2 3. Address Space External Address Space The external address space is classified into CS areas (CS0 to CS7) and SDRAM area (SDCS). CS areas can be divided into up to eight areas (CS0 to SC7) corresponding to the CSn# signal to be output from the CSn# pin. Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) and SDRAM area (SDCS) in on-chip ROM disabled extended mode.
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RX63N Group, RX631 Group 4. 4. I/O Registers I/O Registers This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on writing to registers are also given at the end. (1) I/O register addresses (address order)  Registers are listed from the lower allocation addresses.  Registers are classified according to module symbols.  The number of access cycles indicates the number of cycles based on the specified reference clock.
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RX63N Group, RX631 Group 4. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] CMP [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
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RX63N Group, RX631 Group 4.1 4. I/O Registers I/O Register Addresses (Address Order) Table 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group Table 4.1 4.
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RX63N Group, RX631 Group 5. Electrical Characteristics 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Absolute Maximum Ratings Conditions: VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Item Symbol Value Unit Power supply voltage VCC, VCC_USB –0.3 to +4.6 V VBATT power supply voltage VBATT –0.3 to +4.6 V Vin –0.3 to VCC + 0.3 V Input voltage (except for ports for 5 V tolerant*1) tolerant*1) Vin –0.3 to +5.8 V Reference power supply voltage VREFH –0.
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RX63N Group, RX631 Group 5.2 5. Electrical Characteristics DC Characteristics Table 5.2 DC Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.
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RX63N Group, RX631 Group Table 5.3 5. Electrical Characteristics DC Characteristics (2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions Output high voltage All output pins VOH VCC – 0.5 — — V IOH = –1 mA Output low voltage All output pins (except for RIIC pins, and ETHERC) VOL — — 0.5 V IOL = 1.0 mA — — 0.4 V IOL = 3.0 mA — — 0.6 — — 0.
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RX63N Group, RX631 Group Table 5.4 5. Electrical Characteristics DC Characteristics (3) (for D and G Versions (-40 ≤ Ta ≤ +85°C)) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Supply current*1 High-speed operating mode Item Symbol Max.*2 Max.
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RX63N Group, RX631 Group Table 5.4 5. Electrical Characteristics DC Characteristics (3) (for D and G Versions (-40 ≤ Ta ≤ +85°C)) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit RAM standby voltage VRAM 2.7 — — V VCC rising gradient SrVCC 8.4 — 20000 µs/V VCC falling gradient*8 SfVCC 8.4 — — µs/V Test Conditions Note 1.
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RX63N Group, RX631 Group 5. Electrical Characteristics DC Characteristics (4) (for G Version (+85 < Ta ≤ +105°C)) Table 5.5 Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Normal *4 ICC *3 Typ. Max.
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RX63N Group, RX631 Group 5. Electrical Characteristics Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLK:BCLK:BCLK pin = 8:4:4:2) ICC Max. = 0.87 × f + 13 (max. operation in high-speed operating mode) ICC Typ. = 0.35 × f + 5 (normal operation in high-speed operating mode) ICC Typ. = 1.
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RX63N Group, RX631 Group Table 5.6 5. Electrical Characteristics DC Characteristics (4) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Permissible total power consumption*1 Symbol Min. Typ. Pd — — Max. Unit 380 mW Test Conditions *2 Note 1. This is the total power consumption of the chip as a whole (including the power consumed by the output buffers). Note 2.
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RX63N Group, RX631 Group 5.3 5. Electrical Characteristics AC Characteristics Table 5.8 Operation Frequency Value (High-Speed Operating Mode) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operation frequency Symbol Min. Typ. Max.
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RX63N Group, RX631 Group Table 5.10 5. Electrical Characteristics Operation Frequency Value (Low-Speed Operating Mode 2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operation frequency Symbol System clock (ICLK) Min. Max. Unit kHz 32 — 143.75 Peripheral module clock (PCLKA) — — 143.75 Peripheral module clock (PCLKB) — — 143.75 FlashIF clock (FCLK) 32 — 143.
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RX63N Group, RX631 Group 5. Electrical Characteristics VCC RES# tRESWP Internal reset tRESWT Figure 5.1 Reset Input Timing at Power-On tRESWD, tRESWS, tRESWF, tRESW RES# Internal reset tRESWT Figure 5.2 Reset Input Timing R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics 5.3.2 Clock Timing Table 5.12 Clock Timing (Except for Sub-Clock Related) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item BCLK pin output cycle time Packages with 177 to 144 pins Symbol Min. Typ. Max. tBcyc 20 — — 40 — — Packages with 100 pins or less Unit Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics Note 1. This is the time until the clock is used after setting P36 and P37 as inputs, and then clearing the main clock oscillator stop bit (MOSCCR.MOSTP) to 0 (selecting operation). Note 2. This is the time until the frequency of oscillation by the HOCO (fHOCO) reaches the range for guaranteed operation after release from the reset state. Note 3. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation.
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RX63N Group, RX631 Group Table 5.13 5. Electrical Characteristics Clock Timing (Sub-Clock Related) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.0 to 3.6 V (for products with 100 pins or more), VBATT = 2.3 to 3.6 V (for the 64-pin product), VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Sub-clock frequency fSUB — 32.768 — kHz Sub-clock oscillator start-up time tSUBOSC — — *1 tSUBOSCWT0 1.8 — 2.
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RX63N Group, RX631 Group 5. Electrical Characteristics MOSCCR.MOSTP tMAINOSC Main clock oscillator output tMAINOSCWT Main clock Figure 5.5 Main Clock Oscillation Start Timing LOCOCR.LCSTP, ILOCOCR.ILCSTP tLOCOWT LOCO, IWDTCLK clock Figure 5.6 LOCO, IWDTCLK Oscillation Start Timing RES# Internal reset tRESWT HOCOCR.HCSTP tHOCOWT1 HOCO clock Figure 5.7 HOCO Oscillation Start Timing (After Reset is Canceled by Setting the OFS1.HOCOEN Bit to 0) RES# Internal reset tRESWT HOCOCR.
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RX63N Group, RX631 Group 5. Electrical Characteristics HOCOPCR.HOCOPCNT HOCOCR.HCSTP tHOCOP Internal power supply for HOCO Figure 5.9 HOCO Power Supply Control Timing MOSCCR.MOSTP tMAINOSC Main clock oscillator output PLLCR2.PLLEN tPLL1 PLL circuit output tPLLWT1 PLL clock Figure 5.10 PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has Settled) MOSCCR.MOSTP tMAINOSC Main clock oscillator output PLLCR2.PLLEN tPLL2 PLL circuit output tPLLWT2 PLL clock Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output tSUBOSCWT0 *1 Sub-clock Note: This is the waiting period obtained by setting the SOCCWTCR.SSTS[4:0] bits. Figure 5.12 Sub-Clock Oscillation Start Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes Table 5.14 Timing of Recovery from Low Power Consumption Modes Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.
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RX63N Group, RX631 Group 5. Electrical Characteristics Oscillator ICLK IRQ Software standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYSC, tSBYHO, tSBYLO Figure 5.13 Software Standby Mode Cancellation Timing Oscillator IRQ Deep software standby reset Internal reset Deep software standby mode tDSBY tDSBYWT Reset exception handling start Figure 5.14 Deep Software Standby Mode Cancellation Timing 5.3.4 Control Signal Timing Table 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics NMI tNMIW Figure 5.15 NMI Interrupt Input Timing IRQ tIRQW Figure 5.16 IRQ Interrupt Input Timing R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics 5.3.5 Bus Timing Table 5.16 Bus Timing (packages with 177 to 144 pins) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, ICLK = 8 to 100 MHz, BCLK pin = 8 to 50 MHz, SDCLK pin = 8 to 50MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF High drive output is selected by the drive capacity control register.
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RX63N Group, RX631 Group Table 5.17 5. Electrical Characteristics Bus Timing (packages with 100 pins or less) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, ICLK = 8 to 100 MHz, BCLK pin = 8 to 50 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF High drive output is selected by the drive capacity control register. Item Symbol Min. Max.
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RX63N Group, RX631 Group 5. Electrical Characteristics Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 Tend TW5 Tn1 Tn2 BCLK pin tAD Address bus tAD tRDS tAD tRDH Address bus/ data bus tALED tALED Address latch (ALE) tRSD tRSD Data read (RD#) Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics CSRWAIT:2 RDON:1 CSROFF:2 CSON:0 TW1 TW2 Tend Tn1 Tn2 BCLK pin Byte write strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tRSD tRSD RD# (Read) tRDS tRDH D31 to D0 (Read) Figure 5.19 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics CSWWAIT:2 WRON:1 WDON:1*1 CSWOFF:2 WDOFF:1*1 CSON:0 TW1 TW2 Tend Tn1 Tn2 BCLK pin Byte write strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tWRD tWRD WR3# to WR0#, WR# (Write) tWDD tWDH D31 to D0 (Write) Note1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.
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RX63N Group, RX631 Group 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 BCLK pin A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait tWTS tWTH tWTS tWTH WAIT# Figure 5.23 External Bus Timing/External Wait Control R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics SDRAM command ACT RD PRA SDCLK pin tAD2 tAD2 Row Address A18 to A0 tAD2 tAD2 tAD2 tAD2 tAD2 Column Address tAD2 AP*1 PRA Command tCSD2 tCSD2 tRASD tRASD tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tWED tWED SDCS# RAS# tCASD tCASD CAS# WE# (High) CKE tDQMD DQMn tRDS2 tRDH2 D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.
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RX63N Group, RX631 Group SDRAM command 5. Electrical Characteristics ACT WR PRA SDCLK pin tAD2 tAD2 Row Address A18 to A0 tAD2 tAD2 tAD2 tAD2 tAD2 Column Address tAD2 AP*1 PRA command tCSD2 tCSD2 tRASD tRASD tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tWED tWED SDCS# RAS# tCASD tCASD tWED tWED CAS# WE# (High) CKE tDQMD DQMn tWDD2 tWDH2 D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.
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RX63N Group, RX631 Group 5.
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RX63N Group, RX631 Group 5.
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RX63N Group, RX631 Group SDRAM command 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics MRS SDRAM command SDCLK pin t AD2 t AD2 t AD2 t AD2 t CSD2 t CSD2 t RASD t RASD t CASD t CASD t WED t WED A18 to A0 AP*1 SDCS# RAS# CAS# WE# (High) CKE DQMn (Hi-Z) D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.29 SDRAM Space Mode Register Set Bus Timing R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group SDRAM command 5. Electrical Characteristics Ts (RFA) (RFS) (RFX) (RFA) SDCLK pin t AD2 t AD2 t AD2 t AD2 A18 to A0 AP*1 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t RASD t RASD t RASD t RASD t RASD t RASD t RASD t CASD t CASD t CASD t CASD t CASD t CASD t CASD SDCS# RAS# CAS# (High) WE# t CKED t CKED CKE t DQMD t DQMD DQMn (Hi-Z) D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics 5.3.6 EXDMAC Timing Table 5.18 EXDMAC Timing Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz, BCLK pin = 8 to 100 MHz, SDCLK pin = 8 to 50 MHz, Ta = Topr High drive output is selected by the drive capacity control register Item EXDMAC Symbol Min. Max. Unit Test Conditions EDREQ setup time tEDRQS 20 — ns Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics 5.3.7 Timing of On-Chip Peripheral Modules Table 5.19 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min. Max. Unit*1 Test Conditions tPRW 1.5 — tPcyc Figure 5.34 tTICW 1.5 — tPcyc Figure 5.35 2.5 — 1.
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RX63N Group, RX631 Group Table 5.20 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*1, VREFH0 = 2.7 V to AVCC0*1, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, PCLK = 8 to 50 MHz, Ta = Topr High drive output is selected by the drive capacity control register. Item RSPI RSPCK clock cycle Master Symbol Min. Max. Unit*2 Test Conditions tSPcyc 2 4096 tPcyc 8 4096 Figure 5.
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RX63N Group, RX631 Group Table 5.21 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (3) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*1, VREFH0 = 2.7 V to AVCC0*1, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, PCLK = 8 to 50 MHz, Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min. Max. Unit*2 Test Conditions tOD — 18 ns Figure 5.43 to Figure 5.
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RX63N Group, RX631 Group Table 5.22 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (4) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Item Simple SPI SCK clock cycle output (master) Symbol Min. Max. Unit*1 Test Conditions tSPcyc 4 65536 tPcyc Figure 5.
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RX63N Group, RX631 Group Table 5.23 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (5) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min.*1,*2 Max.* Unit Test Conditions tSCL 6(12) × tIICcyc + 1300 — ns Figure 5.
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RX63N Group, RX631 Group Table 5.24 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (6) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min.*, *2 Max.* Unit SCL input cycle time tSCL 6(12) × tIICcyc + 240 — ns Item RIIC (Fast-mode+) ICFER.
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RX63N Group, RX631 Group Table 5.25 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (7) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V ICLK = 12.5 to 100 MHz, Ta = Topr High drive output is selected by the drive capacity control register. Item ETHERC(RMII) ETHERC(MII) Symbol Min. Max. Unit REF50CK cycle time Tck 20 — ns REF50CK frequency Typ.
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RX63N Group, RX631 Group Table 5.26 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (8) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.
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RX63N Group, RX631 Group 5. Electrical Characteristics PCLK MTCLKA to MTCLKH tTCKWL Figure 5.36 tTCKWH MTU Clock Input Timing PCLK POEn# input tPOEW Figure 5.37 POE# Input Timing PCLK TMCI0 to TMCI3 tTMCWL Figure 5.38 tTMCWH 8-Bit Timer Clock Input Timing tSCKW tSCKr tSCKf SCKn (n = 0 to 12) tScyc Figure 5.39 SCK Clock Input Timing R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics SCKn tTXD TxDn tRXS tRXH RxDn n = 0 to 12 Figure 5.40 SCI Input/Output Timing: Clock Synchronous Mode PCLK ADTRG0#-A/B ADTRG1# tTRGW Figure 5.
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RX63N Group, RX631 Group RSPI 5. Electrical Characteristics Simple SPI tTD SSLm0 to SSLm3 output tLEAD RSPCKm CPOL = 0 output SCKn CKPOL = 0 output RSPCKm CPOL = 1 output SCKn CKPOL = 1 output tLAG tSSLr, tSSLf tSU MISOm input SMISOm input MOSIm output SMOSIm output (m = A to C) (n = 0 to 12) tH MSB IN DATA tDr, tDf tOH MSB OUT Figure 5.
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RX63N Group, RX631 Group RSPI Simple SPI SSLm0 input SSn# input RSPCKm CPOL = 0 input SCKn CKPOL = 0 input RSPCKm CPOL = 1 input SCKn CKPOL = 1 input 5. Electrical Characteristics tTD tLEAD tLAG tSA MISOm output SMISOm output MOSIm input SMOSIm input (m = A to C) (n = 0 to 12) tOH MSB OUT tSU Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics VIH SDA0 to SDA3 VIL tBUF tSCLH tSTAS tSTAH tSTOS tSP SCL0 to SCL3 P *1 P *1 Sr *1 S *1 tSCLL tSr tSf tSDAS tSCL tSDAH Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 5.47 Test conditions VIH = VCC × 0.7, VIL = VCC × 0.
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RX63N Group, RX631 Group 5. Electrical Characteristics REF50CK Tsu Thd RMII_CRS_DV Thd Tsu RMII_RXD1 RMII_RXD0 Preamble DATA CRC SFD RMII_RX_ER Figure 5.50 L RMII Reception Timing (Normal Operation) REF50CK RMII_CRS_DV RMII_RXD1 RMII_RXD0 Preamble SFD DATA xxxx Thd Tsu RMII_RX_ER Figure 5.51 RMII Reception Timing (Error Occurrence) REF50CK tWOLd ET_WOL Figure 5.52 WOL Output Timing (RMII) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics ET_TX_CLK tTENd ET_TX_EN tMTDd ET_ETXD[3:0] Preamble SFD DATA CRC ET_TX_ER tCRSs tCRSh ET_CRS ET_COL Figure 5.53 MII Transmission Timing (Normal Operation) ET_TX_CLK ET_TX_EN ET_ETXD[3:0] Preamble JAM ET_TX_ER ET_CRS tCOLs tCOLh ET_COL Figure 5.54 MII Transmission Timing (Conflict Occurrence) ET_RX_CLK tRDVs tRDVn ET_RX_DV tMRDh tMRDs ET_ERXD[3:0] Preamble SFD DATA CRC ET_RX_ER Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics ET_RX_CLK ET_RX_DV Preamble ET_ERXD[3:0] SFD DATA XXXX tRERh tRERs ET_RX_ER Figure 5.56 MII Reception Timing (Error Occurrence) ET_RX_CLK tWOLd ET_WOL Figure 5.57 WOL Output Timing (MII) PIXCLK tSYNCSETUP tSYNCHOLD VSYNC tSYNCSETUP tSYNCHOLD HSYNC tDATAHOLD tDATASETUP PIXD7 to PIXD0 Figure 5.58 PDC Timing tPIXcyc tPIXH PIXCLK pin input tPIXL Figure 5.59 PDC Input Clock Characteristic R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics tPCKcyc tPCKH tPCKf PCKO pin output tPCKL tPCKr Output load condition: VOH = VCC × 0.7, VOL= VCC × 0.3, IOH = -0.1 mA, IOL= 1.0 mA, C = 15 pF Figure 5.60 PDC Output Clock Characteristic R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5.4 5. Electrical Characteristics USB Characteristics Table 5.27 On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 24 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Item Input characteristics Output characteristics Symbol Min. Max. Unit Input high level voltage VIH 2.
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RX63N Group, RX631 Group 5.5 5. Electrical Characteristics A/D Conversion Characteristics Table 5.28 10-Bit A/D Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr Item Resolution Conversion time*1 (Operation at PCLK = 50 MHz) enough*2 Min. Typ. Max. Unit — 3.0 — 10 Bit (2.5)*3 — — µs Test Conditions Sampling in 125 states With 0.
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RX63N Group, RX631 Group Table 5.29 5. Electrical Characteristics 12-Bit A/D Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr Item Resolution Conversion time*1 (Operation at PCLK = 50 MHz) Min. Typ. Max. Unit — Test Conditions — 12 Bit (0.4)*2 — — µs Sampling in 20 states AN0 to AN7 Permissible signal source impedance (max.) = 1.0 kΩ 1.
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RX63N Group, RX631 Group 5.6 5. Electrical Characteristics D/A Conversion Characteristics Table 5.31 D/A Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to VCC VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time — — 3.0 µs 20-pF capacitive load Absolute accuracy — ±2.0 ±4.0 LSB 2-MΩ resistive load RO output resistance 5.7 Test Conditions — — ±3.
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RX63N Group, RX631 Group 5.8 5. Electrical Characteristics Power-on Reset Circuit and Voltage Detection Circuit Characteristics Table 5.33 Power-on Reset Circuit and Voltage Detection Circuit Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Voltage detection level Power-on reset (POR) Low power consumption function disabled Symbol Min. Typ. Max. Unit Test Conditions VPOR 2.5 2.
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RX63N Group, RX631 Group 5. Electrical Characteristics tVOFF VCC Vdet0 Internal reset signal (active-low) tdet Figure 5.64 tLVD0 Voltage Detection Circuit Timing (Vdet0) tVOFF VCC VLVH Vdet1 LVD1E Td(E-A) LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal (active-low) When LVD1RN = L tdet tdet tLVD1 When LVD1RN = H tLVD1 Figure 5.65 Voltage Detection Circuit Timing (Vdet1) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5. Electrical Characteristics tVOFF VCC VLVH Vdet2 LVD2E Td(E-A) LVD2 Comparator output LVD2CMPE LVD2MON Internal reset signal (active-low) When LVD2RN = L tdet tdet tLVD2 When LVD2RN = H tLVD2 Figure 5.66 Voltage Detection Circuit Timing (Vdet2) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group 5.9 5. Electrical Characteristics Oscillation Stop Detection Timing Table 5.34 Oscillation Stop Detection Circuit Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions Detection time tdr — — 1 ms Figure 5.67 Main clock or PLL clock tdr OSTDSR.OSTDF LOCO clock ICLK Figure 5.
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RX63N Group, RX631 Group 5.10 5. Electrical Characteristics Battery Backup Function Characteristics Table 5.35 Battery Backup Function Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.0 to 3.6 V (for products with 100 pins or more), VBATT = 2.3 to 3.6 V (for the 64-pin product) VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Symbol Min. Typ. Max.
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RX63N Group, RX631 Group 5.11 5. Electrical Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.36 ROM (Flash Memory for Code Storage) Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.
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RX63N Group, RX631 Group 5.12 5. Electrical Characteristics E2 Flash Characteristics Table 5.38 E2 Flash Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.7V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0V Temperature range for the programming/erasure operation: Ta = Topr Item Symbol min typ max Unit Condition Reprogram/erasure cycle*1 NDPEC 100000 — — Times Data hold time tDDRP 30*2 — — Year Ta = +85°C Note 1.
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RX63N Group, RX631 Group 5. Electrical Characteristics • Suspension during programming FCU command Program Suspend tSPD FSTATR0.FRDY Ready Programming pulse Not Ready Ready Programming • Suspension during erasure in suspend priority mode FCU command Erase Suspend Resume Suspend tSESD1 FSTATR0.FRDY Ready Erasure pulse Not Ready tSESD2 Ready Erasing Not Ready Erasing • Suspension during erasure in erasure priority mode FCU command Erase FSTATR0.
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RX63N Group, RX631 Group 5.13 5. Electrical Characteristics Boundary Scan Table 5.40 Boundary Scan Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6V, VREFH0 = 2.7V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0V Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions TCK clock cycle time tTCKcyc 100 ― ― ns Figure 5.
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RX63N Group, RX631 Group 5. Electrical Characteristics TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 5.72 Boundary Scan Input/Output Timing R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas Electronics Corporation website. JEITA Package Code P-TFLGA177-8x8-0.50 RENESAS Code PTLG0177KA-A Previous Code 177F0E-A MASS[Typ.] 0.
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RX63N Group, RX631 Group Appendix 1. Package Dimensions Figure B 176-pin LFBGA (PLBG0176GA-A) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group JEITA Package Code P-LFQFP176-24x24-0.50 RENESAS Code PLQP0176KB-A Appendix 1. Package Dimensions Previous Code MASS[Typ.] 176P6Q-A/FP-176E/FP-176EV 1.8g HD *1 D 132 89 133 88 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX63N Group, RX631 Group JEITA Package Code P-TFLGA145-7x7-0.50 RENESAS Code PTLG0145KA-A Appendix 1. Package Dimensions Previous Code 145F0G MASS[Typ.] 0.1g w S B b1 D S AB b S AB w S A ZD A e e N M L K J E H G F E D C B y S x4 v Index mark (Laser mark) ZE A 1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y ZD ZE Nom Max 7.0 7.0 0.15 0.20 1.05 0.5 0.21 0.25 0.29 0.29 0.34 0.39 0.08 0.10 0.5 0.
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RX63N Group, RX631 Group JEITA Package Code P-LFQFP144-20x20-0.50 Appendix 1. Package Dimensions RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX63N Group, RX631 Group JEITA Package Code P-TFLGA100-7x7-0.65 RENESAS Code PTLG0100JA-A Appendix 1. Package Dimensions Previous Code 100F0G MASS[Typ.] 0.1g w S B φ b1 D φ× M S φb w S A ZD AB e A e A AB φ× M S K J H G B E F E D C B ×4 y S v Index mark (Laser mark) S ZE A 1 2 3 Index mark 4 5 6 7 8 9 10 Reference Dimension in Millimeters Symbol Min Nom D 7.0 E 7.0 v w A e 0.65 b 0.31 0.35 b1 0.385 0.435 x y ZD 0.575 ZE 0.575 Max 0.15 0.20 1.05 0.39 0.485 0.08 0.
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RX63N Group, RX631 Group JEITA Package Code P-LFQFP100-14x14-0.50 Appendix 1. Package Dimensions RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX63N Group, RX631 Group JEITA Package Code P-TFLGA64-6x6-0.65 Appendix 1. Package Dimensions RENESAS Code PTLG0064JA-A Previous Code 64F0G MASS[Typ.] 0.07g w S B b1 S AB b D S w S A AB e A e H G F E E D C B A y S x4 v Index mark (Laser mark) 1 2 3 Index mark 4 5 6 7 8 Reference Symbol D E v w A e b b1 x y Dimension in Millimeters Min Nom Max 6.0 6.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10 Figure H 64-pin TFLGA (PTLG0064JA-A) R01DS0098EJ0180 Rev.1.
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RX63N Group, RX631 Group JEITA Package Code P-LFQFP64-10x10-0.50 Appendix 1. Package Dimensions RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D 48 33 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX63N Group, RX631 Group JEITA Package Code P-LFQFP48-7x7-0.50 Appendix 1. Package Dimensions RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 37 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 24 bp c c1 *2 E HE b1 Reference Dimension in Millimeters Symbol 48 13 1 ZE Terminal cross section 12 c A F A2 Index mark ZD S A1 L D E A2 HD HE A A1 bp b1 c c1 e *3 bp Detail F x 8.8 8.
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REVISION HISTORY RX63N Group, RX631 Group REVISION HISTORY REVISION HISTORY Rev. Date RX63N Group, RX631 Group Datasheet Description Summary Page 0.50 May 13. 2011 — 0.90 Dec 27. 2011 All First Edition issued — Package added (177-pin TFLGA, 176-pin LFBGA, 145-pin TFLGA), module name changed — Interrupt Controller (ICUb) module name changed 1. Overview 2 to 6 Table 1.1 Outline of Specifications, Reset, Realtime clock, Temperature sensor, Power supply voltage, changed 8 to 10 Table 1.
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RX63N Group, RX631 Group Rev. 1.60 REVISION HISTORY Description Summary Date Page Mar 13. 2013 Feature 1 Changed 1. Overview 2 to 7 Table 1.1 Outline of Specifications: changed, note added 8 Table1.2 Comparison of Functions for Different Packages in the RX63N/RX631 Group, changed 9 to 15 Table 1.3 List of Products, changed 16 Figure 1.1 How to Read the Product Part No., changed 17 Figure 1.2 Block Diagram, changed 24 to 32 Figure 1.3 to Figure 1.
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RX63N Group, RX631 Group Rev. 1.70 Date Oct 08. 2013 Page 80 to 127 REVISION HISTORY Description Summary Table 4.1 List of I/O Registers (Address Order), changed 5. Electrical Characteristics 131, 132 Table 5.4 DC Characteristics (3), changed, Note. 9, Note. 10, added 133 Table 5.6 Permissible Output Currents, changed 139 Table 5.12 Clock Timing (Sub-Clock Related), Note 3, added 167 Table 5.25 Timing of On-Chip Peripheral Modules (8), added 175 Figure 5.58 PDC Timing, added 175 Figure 5.
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RX63N Group, RX631 Group REVISION HISTORY Classifications - Items with Technical Update document number: Changes according to the corresponding issued Technical Update - Items without Technical Update document number: Minor changes that do not require Technical Update to be issued Rev. Date Description Summary Page Classification 1.80 May 13. 2014 Features 1 Operating temp. range chaged, Unique ID added 1. Overview 2 to 7 8 9 to 16 17 19, 23 Table 1.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual.
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.