Datasheet

R01DS0060EJ0160 Rev.1.60 Page 126 of 154
May 19, 2014
RX630 Group 5. Electrical Characteristics
Note: t
IICcyc
: RIIC internal reference clock (IIC) Cycle, t
Pcyc
: PCLK cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
Figure 5.24 I/O Port Input Timing
Table 5.20 Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min.*
,
*
2
Max.* Unit
Test
Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time t
SCL
6(12) × t
IICcyc
+ 240 — ns Figure
5.37
SCL input high pulse width t
SCLH
3(6) × t
IICcyc
+ 120 — ns
SCL input low pulse width t
SCLL
3(6) × t
IICcyc
+ 120 — ns
SCL, SDA input rise time t
Sr
— 120 ns
SCL, SDA input fall time t
Sf
— 120 ns
SCL, SDA input spike pulse removal time t
SP
01(4) × t
IICcyc
ns
SDA input bus free time t
BUF
3(6) × t
IICcyc
+ 120 — ns
Start condition input hold time t
STAH
t
IICcyc
+ 120 — ns
Restart condition input setup time t
STAS
120 — ns
Stop condition input setup time t
STOS
120 — ns
Data input setup time t
SDAS
t
IICcyc
+ 120 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 550 pF
Simple IIC
(Standard-mode)
SDA input rise time t
Sr
— 1000 ns
SDA input fall time t
Sf
— 300 ns
SDA input spike pulse removal time t
SP
04 × t
IICcyc
ns
Data input setup time t
SDAS
250 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF
Simple IIC
(Fast-mode)
SCL, SDA input rise time t
Sr
20 + 0.1C
b
300 ns
SCL, SDA input fall time t
Sf
20 + 0.1C
b
300 ns
SCL, SDA input spike pulse removal time t
SP
04 × t
IICcyc
ns
Data input setup time t
SDAS
100 — ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 400 pF
Port
PCLK
t
PRW