Datasheet

R01DS0060EJ0160 Rev.1.60 Page 124 of 154
May 19, 2014
RX630 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
Table 5.18 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit*
1
Test Conditions
Simple
SPI
SCK clock cycle output (master) t
SPcyc
4 65536 t
Pcyc
Figure 5.32
SCK clock cycle input (slave) 8 65536
SCK clock high pulse width t
SPCKWH
0.4 0.6 t
SPcyc
SCK clock low pulse width t
SPCKWL
0.4 0.6 t
SPcyc
SCK clock rise/fall time t
SPCKr,
t
SPCKf
—20ns
Data input setup time t
SU
40 — ns Figure 5.33 to
Figure 5.36
Data input hold time t
H
40 — ns
SS input setup time t
LEAD
1—t
SPcyc
SS input hold time t
LAG
1—t
SPcyc
Data output delay time t
OD
—40ns
Data output hold time t
OH
–10 — ns
Data rise/fall time t
Dr,
t
Df
—20ns
SS input rise/fall time t
SSLr,
t
SSLf
—20ns
Slave access time t
SA
—5 t
Pcyc
Figure 5.35 and
Figure 5.36
Slave output release time t
REL
—5 t
Pcyc