Datasheet

R01DS0060EJ0160 Rev.1.60 Page 123 of 154
May 19, 2014
RX630 Group 5. Electrical Characteristics
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t
Pcyc
: PCLK cycle
Table 5.17 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*
1
, VREFH0 = 3.0 V to AVCC0*
1
,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T
a
= T
opr
High drive output is selected by the drive capacity control register.
Item Symbol Min. Max. Unit*
2
Test Conditions
RSPI RSPCK clock cycle Master t
SPcyc
2 4096 t
Pcyc
C = 30
P
F,
Figure 5.32
Slave 8 4096
RSPCK clock high pulse
width
Master t
SPCKWH
(t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2 – 3
—ns
Slave (t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2
—
RSPCK clock low pulse
width
Master t
SPCKWL
(t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2 – 3
—ns
Slave (t
SPcyc
– t
SPCKR
– t
SPCKF
) / 2
—
RSPCK clock rise/fall time Output t
SPCKr,
t
SPCKf
—5ns
Input — 1 μs
Data input setup time Master VCC
 3.0 V t
SU
15 — ns C = 30
P
F,
Figure 5.33 to
Figure 5.36
VCC < 3.0 V 20 —
Slave 20
– t
Pcyc
—
Data input hold time Master t
H
0—ns
Slave 20 + 2 × t
Pcyc
—
SSL setup time Master t
LEAD
18t
SPcyc
Slave 4 — t
Pcyc
SSL hold time Master t
LAG
18t
SPcyc
Slave 4 — t
Pcyc
Data output delay time Master t
OD
—18ns
Slave — 3 × t
Pcyc
+ 40
Data output hold time Master t
OH
0—ns
Slave 0 —
Successive transmission
delay time
Master t
TD
t
SPcyc
+ 2 × t
Pcyc
8 × t
SPcyc
+ 2 × t
Pcyc
ns
Slave 4 × t
Pcyc
—
MOSI and MISO rise/
fall time
Output t
Dr,
t
Df
—5ns
Input — 1 μs
SSL rise/fall time Output t
SSLr,
t
SSLf
—5ns
Input — 1 μs
Slave access time t
SA
—4t
Pcyc
C = 30
P
F,
Figure 5.35 and
Figure 5.36
Slave output release time t
REL
—3t
Pcyc