Datasheet

R01DS0060EJ0160 Rev.1.60 Page 11 of 154
May 19, 2014
RX630 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows a block diagram.
Figure 1.2 Block Diagram
ICUb: Interrupt controller
DTCa: Data transfer controller
DMACA: DMA controller
BSC: Bus controller
WDTA: Watchdog timer
IWDTa: Independent watchdog timer
CRC: CRC (cyclic redundancy check) calculator
SCIc, SCId: Serial communications interface
USBa: USB 2.0 function module
RSPI: Serial peripheral interface
MPU: Memory protection unit
CAN: CAN module
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
TPUa: 16-bit timer pulse unit
PPG: Programmable pulse generator
TMR: 8-bit timer
CMT: Compare match timer
RTCa: Realtime clock
RIIC: I
2
C bus interface
IEB: IEBus controller
External busBSC
Operand bus
Instruction bus
Internal main bus 1
Clock
generation
circuit
RX CPU
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
10-bit ADC × 8 channels
12-bit ADC × 21 channels
MTU2a × 6 channels
10-bit DAC × 2 channels
SCIc × 12 channels
WDTA
RIIC × 4 channels
E2 DataFlash
CRC
IWDTa
USBa × 1 port
CAN × 3 channels
RTCa
POE2a
TPUa × 6 channels (unit 1)
IEB
CMT × 2 channels (unit 1)
CMT × 2 channels (unit 0)
TMR × 2 channels (unit 1)
TMR × 2 channels (unit 0)
PPG (unit 1)
PPG (unit 0)
RSPI (unit 1)
RSPI (unit 0)
Internal peripheral buses 1 to 6
Internal main bus 2
DTCa
DMACA ×
4 channels
ICUb
Temperature sensor
TPUa × 6 channels (unit 0)
RSPI (unit 2)
SCId × 1 channel
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
MPU