Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 32-Bit 100 MHz I/O number 117

RX630 Group

Renesas MCUs

DATASHEET

R01DS0060EJ0160 Rev.1.60 Page 1 of 154

May 19, 2014

Features

■ 32-bit RX CPU core

 Max. operating frequency: 100 MHz

Capable of 165 DMIPS in operation at 100 MHz

 Single precision 32-bit IEEE-754 floating point

 Two types of multiply-and-accumulation unit (between memories

and between registers)

 32-bit multiplier (fastest instruction execution takes one CPU

clock cycle)

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 Two types of debugging interfaces: JTAG and FINE (two-line)

■ Low-power design and architecture

 Operation from a single 2.7- to 3.6-V supply

 Low power consumption: A product that supports all peripheral

functions draws only 500 μA/MHz.

 RTC is capable of operation from a dedicated power supply (min.

operating voltage: 2.3 V).

 Four low-power modes

■ On-chip main flash memory, no wait states

 100-MHz operation, 10-ns read cycle (no wait states)

 384-Kbyte to 2-Mbyte capacities

 User code is programmable by on-board or off-board

programming.

■ On-chip data flash memory

 Max. 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM, no wait states

 32- to 128-Kbyte capacities

 For instructions and operands

 Can provide backup on deep software standby

■ DMA

 DMAC: Incorporates four channels

 DTC

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 External crystal oscillator or internal PLL for operation at 4 to 16

MHz

 Internal 125-kHz LOCO and 50-MHz HOCO

 125-kHz clock for the IWDT

 Frequency of the oscillator for sub-clock generation: 32 kHz

■ Real-time clock

 Adjustment functions (30 seconds, leap year, and error)

 Time capture function

(for capturing times in response to event-signal input on external

pins)

■ Independent watchdog timer

 125-kHz LOCO clock operation

■ Useful functions for IEC60730 compliance

 Oscillation-stop detection, frequency measurement, CRC, IWDT,

self-diagnostic function for the A/D converter, etc.

■ Up to 22 communications interfaces

 USB 2.0 full-speed function interface (1 channel)

 CAN (compliant with ISO11898-1), incorporating 32 mailboxes

(up to 3 channels)

 SCI with multiple functionalities (up to 13 channels)

Choose from among asynchronous mode, clock-synchronous

mode, smart-card interface mode, simple SPI, simple I

C, and

extended serial mode.

 I

C bus interface for transfer at up to 1 Mbps (up to 4 channels)

 RSPI for high-speed transfer (up to 3 channels)

■ External address space

 8 CS areas (8 × 16 Mbytes)

 Multiplexed address data or separate address lines are selectable

per area.

 8-, 16-, or 32-bit bus space is selectable per area

■ Up to 20 extended-function timers

 16-bit MTU2: input capture, output capture, complementary PWM

output, phase-counting mode (6 channels)

 16-bit TPU: input capture, output capture, phase-counting mode

(12 channels)

 8-bit TMR (4 channels)

 16-bit compare-match timers (4 channels)

■ A/D converter for 1-MHz operation

 Up to 21 12-bit channels, and incorporating 1 sample-and-hold

circuit

 Up to 8 10-bit channels, and incorporating 1 sample-and-hold

circuit



Addition of results of A/D conversion (in the 12-bit A/D converter)

 self-diagnosis (for the 10-bit A/D converter)

■ 10-bit D/A converter: 2 channels

■ Temperature sensor for measuring temperature

within the chip

■ Register write protection function can protect

values in important registers against overwriting.

■ Up to 148 general I/O port pins for GPIO

 5-V tolerance, open drain, input pull-up, switchable driving ability

■ Unique ID

 16-byte ID code is provided for each chip (only for the G version)

■ Operating temp. range

 D version: -40 to +85°C

 G version: -40 to +105°C

PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch

PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch

PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch

PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch

PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch

PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch

PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch

PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch

100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,

up to 2-MB flash memory, USB 2.0 full-speed function interface,

CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces

R01DS0060EJ0160

Rev.1.60

May 19, 2014

Features

Summary of content (156 pages)

PAGE 1
Features DATASHEET RX630 Group Renesas MCUs R01DS0060EJ0160 Rev.1.60 May 19, 2014 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, USB 2.0 full-speed function interface, CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces Features PLQP0176KB-A PLQP0144KA-A PLQP0100KB-A PLQP0080KB-A ■ 32-bit RX CPU core  Max.
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RX630 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.
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RX630 Group Table 1.1 1.
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RX630 Group Table 1.1 1.
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RX630 Group Table 1.1 1. Overview Outline of Specifications (4/5) Classification Module/Function Description Communication function USB 2.
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RX630 Group Table 1.1 Classification 1. Overview Outline of Specifications (5/5) Module/Function Description 10-bit A/D converter (ADb)     D/A converter (DAa)  2 channels  10-bit resolution  Output voltage: 0 V to VREFH Temperature sensor  1 channel  Precision: ± 1 ºC  The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
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RX630 Group Table 1.2 1. Overview Comparison of Functions for Different Packages Functions RX630 Group 177 Pins, 176 Pins Package External bus External bus width DMA DMA controller Timers 16-bit timer pulse unit 145 Pins, 144 Pins 100 Pins 32 bits 16 bits Supported Ch. 0 to 11 Ch. 0 to 5 Multi-function timer pulse unit 2 Ch. 0 to 5 Port output enable 2 Supported Programmable pulse generator Ch. 0 and 1 8-bit timers Ch. 0 to 3 Compare match timer Ch.
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RX630 Group 1.2 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part number. Table 1.3 List of Products (1/2) Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp.
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RX630 Group Table 1.3 1. Overview List of Products (2/2) RAM Capacity E2 Data Flash Operating Frequency (Max.) Operating Temp. Range Part No. RX630 (D version) R5F5630DDDLK PTLG0145KA-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz -40 to +85°C R5F5630DCDFC PLQP0176KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz -40 to +85°C RX630 (G version) *2 Package ROM Capacity Group R5F5630DDDFC PLQP0176KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz -40 to +85°C R5F5630DCDBG PLBG0176GA-A 1.
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RX630 Group R 5 F 1. Overview 5 6 3 0 7 C D F N Package type, num ber of pins, and pin pitch F C: LQ FP/176/0.50 BG : LF BG A/176/0.80 LC : T FLG A/177/0.50 F B: LQ FP/144/0.50 LK: T FLG A/145/0.50 F P: LQ FP/100/0.50 LA: T FLG A/100/0.50 F N: LQ FP/80/0.50 D : O perating tem perature range: -40 to +85°C G: Operating temperature range : -40 to +105°C C : C AN m odule not included D : C AN m odule included R O M , R AM , and E2 data flash capacity E: 2 M bytes/128 Kbytes/32 Kbytes D : 1.
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RX630 Group 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram. E2 DataFlash WDTA IWDTa CRC SCIc × 12 channels SCId × 1 channel USBa × 1 port RSPI (unit 0) RSPI (unit 1) Port 1 RSPI (unit 2) Port 2 Internal peripheral buses 1 to 6 CAN × 3 channels MTU2a × 6 channels TPUa × 6 channels (unit 0) Operand bus Internal main bus 1 MPU Clock generation circuit ICUb: DTCa: DMACA: BSC: WDTA: IWDTa: CRC: SCIc, SCId: USBa: RSPI: MPU: Figure 1.
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RX630 Group 1.4 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/5) Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-µF capacitor. The capacitor should be placed close to the pin VCL Input Connect this pin to VSS via a 0.1-F capacitor. The capacitor should be placed close to the pin Clock VSS Input Ground pin.
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RX630 Group Table 1.4 1.
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RX630 Group Table 1.4 1.
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RX630 Group Table 1.4 1.
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RX630 Group Table 1.4 1.
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RX630 Group 1.5 1. Overview Pin Assignments Figure 1.3 to Figure 1.10 show the pin assignments. Table 1.5 to Table 1.11 show the lists of pins and pin functions.
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RX630 Group 1.
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1.
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RX630 Group 1.
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PA3 VSS PA4 VCC PA5 PA6 PA7 PB0 P71 P72 PB1 PB2 PB3 PB4 PB5 PB6 PB7 P73 PL0 PC0 PL1 PC1 94 92 91 90 89 88 87 85 84 83 81 79 77 76 75 74 73 PA1 PA2 96 78 PA0 97 80 P66 P67 99 82 P65 100 86 PE7 101 93 PE6 102 95 P70 PK5 104 98 PE5 PK4 103 PE4 106 105 PE3 107 1.
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RX630 Group 1.
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PE3 PE4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 VCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 76 50 PE1 77 49 PC2 PC3 PE0 78 48 PC4 PD7 79 47 PC5 PD6 80 46 PC6 PD5 81 45 PC7 PD4 82 44 P50 PD3 83 43 P51 PD2 84 42 P52 PD1 85 41 P53 PD0 86 40 P54 P47 87 39 P55 P46 88 38 VSS_USB P45 89 37 USB0_DP P44 90 36 USB0_DM P43 91 35 V
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PE3 PE4 PE5 PA0 PA1 PA2 PA3 PA4 PA5 PA6 VSS PB0 VCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PE2 61 40 PC2 PE1 62 39 PC3 PE0 63 38 PC4 PD2 64 37 PC5 PD1 65 36 PC6 PD0 66 35 PC7 P47 67 34 P54 P46 68 33 P55 P45 69 32 VSS_USB P44 70 31 USB0_DP P43 71 30 USB0_DM P42 72 29 VCC_USB P41 73 28 P12 VREFL0 74 27 P13 P40 75 26 P14 VREFH0 76 25 P15 AVCC0 77 24 P16 P07 78 2
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RX630 Group Table 1.5 1.
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RX630 Group Table 1.5 1.
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RX630 Group Table 1.5 1.
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RX630 Group Table 1.5 1.
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RX630 Group Table 1.5 1.
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RX630 Group Table 1.6 Pin Number 1.
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RX630 Group Table 1.6 Pin Number 176-Pin LQFP 1.
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RX630 Group Table 1.6 Pin Number 176-Pin LQFP 1.
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RX630 Group Table 1.6 Pin Number 176-Pin LQFP 1.
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RX630 Group Table 1.6 Pin Number 176-Pin LQFP 1.
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RX630 Group Table 1.7 Pin Number 1.
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RX630 Group Table 1.7 Pin Number 1.
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RX630 Group Table 1.7 Pin Number 145-Pin TFLGA 1.
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RX630 Group Table 1.7 Pin Number 145-Pin TFLGA 1.
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RX630 Group Table 1.8 Pin Number 1.
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RX630 Group Table 1.8 Pin Number 144-Pin LQFP 1.
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RX630 Group Table 1.8 Pin Number 144-Pin LQFP 1.
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RX630 Group Table 1.8 Pin Number 144-Pin LQFP 1.
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RX630 Group Table 1.9 Pin Number 100-Pin TFLGA 1.
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RX630 Group Table 1.9 Pin Number 1.
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RX630 Group Table 1.9 Pin Number 100-Pin TFLGA 1.
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RX630 Group Table 1.10 Pin Number 1.
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RX630 Group Table 1.10 Pin Number 100-Pin LQFP 1.
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RX630 Group Table 1.10 Pin Number 100-Pin LQFP 1.
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RX630 Group Table 1.11 Pin Number 1.
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RX630 Group Table 1.11 Pin Number 100-Pin LQFP 1.
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RX630 Group Table 1.11 Pin Number 100-Pin LQFP 1. Overview List of Pins and Pin Functions (80-Pin LQFP) (3/3) Power Supply Clock System Control 73 74 76 VREFH0 77 AVCC0 78 80 Communications (MTU, TPU, TMR, PPG, RTC, POE) (SCIc, SCId, RSPI, RIIC, CAN, IEB, USB) Interrupt S12AD, AD, DA P41 IRQ9-DS AN001 P40 IRQ8-DS AN000 P07 IRQ15 ADTRG0# P05 IRQ13 DA1 I/O Port VREFL0 75 79 Timer AVSS0 R01DS0060EJ0160 Rev.1.
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RX630 Group 2. 2. CPU CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions.
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RX630 Group 2.1 2. CPU General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.
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RX630 Group 2.3 (1) 2. CPU Register Associated with DSP Instructions Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator.
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RX630 Group 3. Address Space 3.1 Address Space 3. Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the operating mode and states of control bits. R01DS0060EJ0160 Rev.1.
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RX630 Group 3.
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RX630 Group 3.2 3. Address Space External Address Space The external address space is divided into up to eight CS areas (CS0 to CS7), each corresponding to the CSn# signal output from a CSn# (n = 0 to 7) pin. Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) in on-chip ROM disabled extended mode.
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RX630 Group 4. 4. I/O Registers I/O Registers This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on writing to registers are also given at the end. (1) I/O register addresses (address order)  Registers are listed from the lower allocation addresses.  Registers are classified according to module symbols.  The number of access cycles indicates the number of cycles based on the specified reference clock.
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RX630 Group 4. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] CMP [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
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RX630 Group 4.1 Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 Address 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group Table 4.1 4.
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RX630 Group 5. Electrical Characteristics 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Absolute Maximum Ratings Conditions: VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Item Symbol Value Unit Power supply voltage VCC, VCC_USB –0.3 to +4.6 V VBATT power supply voltage VBATT –0.3 to +4.6 V Vin –0.3 to VCC +0.3 V Input voltage (except for ports for 5 V Input voltage (ports for 5 V tolerant*1) tolerant*1) Vin –0.3 to +5.
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RX630 Group 5.2 5. Electrical Characteristics DC Characteristics Table 5.2 DC Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.
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RX630 Group Table 5.3 5. Electrical Characteristics DC Characteristics (2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions Output high voltage All output pins VOH VCC – 0.5 — — V IOH = –1 mA Output low voltage All output pins (except for RIIC pins) VOL — — 0.5 V IOL = 1.0 mA — — 0.4 V IOL = 3.0 mA — — 0.6 — — 0.4 — 0.
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RX630 Group 5. Electrical Characteristics DC Characteristics (3) (for D and G Versions (-40 ≤ Ta ≤ +85°C)) Table 5.4 Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item High-speed operating mode Supply current*1 Normal ICC *3 Typ. Max.
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RX630 Group 5. Electrical Characteristics DC Characteristics (4) (for G Version (+85 < Ta ≤ +105°C)) Table 5.5 Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item High-speed operating mode Supply current*1 Normal ICC *3 Typ. Max.
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RX630 Group Table 5.6 5. Electrical Characteristics Permissible Output Currents Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Permissible output low current (average value per pin) Permissible output low current (max.
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RX630 Group 5.3 5. Electrical Characteristics AC Characteristics Table 5.7 Operation Frequency Value (High-Speed Operating Mode) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operation frequency Symbol Min. Typ. Max.
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RX630 Group 5. Electrical Characteristics 5.3.1 Reset Timing Table 5.10 Reset Timing Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Symbol Min. Typ. Max. Unit Test Conditions tRESWP 2 — — ms Figure 5.1 Deep software standby mode tRESWD 1 — — ms Figure 5.
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RX630 Group 5. Electrical Characteristics 5.3.2 Clock Timing Table 5.11 Clock Timing (Except for Sub-Clock Related) Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Symbol Min. Typ. Max. Unit Test Conditions BCLK pin output cycle time tBcyc 40 — — ns Figure 5.
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RX630 Group Table 5.12 5. Electrical Characteristics Clock Timing (Sub-Clock Related) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr Item Sub-clock oscillator oscillation frequency Symbol Min. Typ. Max. Unit fSUB — 32.768 — kHz s Sub-clock oscillation stabilization time tSUBOSC — — *1 Sub-clock oscillation stabilization wait offset time*2 tSUBOSCWT0 1.8 — 2.
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RX630 Group 5. Electrical Characteristics MOSCCR.MOSTP tMAINOSC Main clock oscillator output tMAINOSCWT Main clock Figure 5.5 Main Clock Oscillation Start Timing LOCOCR.LCSTP, ILOCOCR.ILCSTP tLOCOWT LOCO, IWDTCLK clock Figure 5.6 LOCO, IWDTCLK Oscillation Start Timing RES# Internal reset tRESWT HOCOCR.HCSTP tHOCOWT1 HOCO clock Figure 5.7 HOCO Oscillation Start Timing (After Reset is Canceled by Setting the OFS1.HOCOEN Bit to 0) RES# Internal reset tRESWT HOCOCR.
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RX630 Group 5. Electrical Characteristics HOCOPCR.HOCOPCNT HOCOCR.HCSTP tHOCOP Internal power supply for HOCO Figure 5.9 HOCO Power Supply Control Timing MOSCCR.MOSTP tMAINOSC Main clock oscillator output PLLCR2.PLLEN tPLL1 PLL circuit output tPLLWT1 PLL clock Figure 5.10 PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has Settled) MOSCCR.MOSTP tMAINOSC Main clock oscillator output PLLCR2.PLLEN tPLL2 PLL circuit output tPLLWT2 PLL clock Figure 5.
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RX630 Group 5. Electrical Characteristics SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output tSUBOSCWT0 *1 Sub-clock Note 1: This is the waiting period obtained by setting the SOCCWTCR.SSTS[4:0] bits. Figure 5.12 Sub-Clock Oscillation Start Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes Table 5.13 Timing of Recovery from Low Power Consumption Modes Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.
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RX630 Group 5. Electrical Characteristics Oscillator ICLK IRQ Software standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYSC, tSBYHO, tSBYLO Figure 5.13 Software Standby Mode Cancellation Timing Oscillator IRQ Deep software standby reset Internal reset Deep software standby mode tDSBY tDSBYWT Reset exception handling start Figure 5.14 Deep Software Standby Mode Cancellation Timing 5.3.4 Control Signal Timing Table 5.
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RX630 Group 5. Electrical Characteristics NMI tNMIW Figure 5.15 NMI Interrupt Input Timing IRQ tIRQW Figure 5.16 IRQ Interrupt Input Timing 5.3.5 Bus Timing Table 5.15 Bus Timing Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, ICLK = 8 to 100 MHz, BCLK = 8 to 50 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, IOH = –1.0 mA, IOL = 1.
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RX630 Group 5. Electrical Characteristics Data cycle Address cycle T a1 T a1 T an T W1 T W2 T W3 T W4 T end T W5 T n1 T n2 BCLK tAD Address bus t AD tRDS tAD tRDH Address bus/ data bus tALED tALED Address latch (ALE) tRSD tRSD Data read (RD#) Figure 5.
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RX630 Group 5. Electrical Characteristics CSRWAIT:2 RDON:1 CSROFF:2 CSON:0 TW1 TW2 Tend Tn1 Tn2 BCLK Byte write strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tRSD tRSD RD# (Read) tRDS tRDH D31 to D0 (Read) Figure 5.19 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized) R01DS0060EJ0160 Rev.1.
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RX630 Group 5. Electrical Characteristics CSWWAIT:2 WRON:1 WDON:1*1 CSWOFF:2 WDOFF:1*1 CSON:0 T W1 T W2 T end T n1 Tn2 BCLK Byte write strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tWRD tWRD WR3# to WR0#, WR# (Write) tWDD tWDH D31 to D0 (Write) Note1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.
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RX630 Group 5.
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RX630 Group 5. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 BCLK A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait tWTS tWTH tWTS tWTH WAIT# Figure 5.23 External Bus Timing/External Wait Control R01DS0060EJ0160 Rev.1.
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RX630 Group 5. Electrical Characteristics 5.3.6 Timing of On-Chip Peripheral Modules Table 5.16 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min. Max. Unit*1 Test Conditions tPRW 1.5 — tPcyc Figure 5.24 tTICW 1.5 — tPcyc Figure 5.25 2.5 — 1.
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RX630 Group Table 5.17 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*1, VREFH0 = 3.0 V to AVCC0*1, VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, PCLK = 8 to 50 MHz, Ta = Topr High drive output is selected by the drive capacity control register. Item RSPI RSPCK clock cycle Master Symbol Min. Max. Unit*2 Test Conditions tSPcyc 2 4096 tPcyc 8 4096 C = 30PF, Figure 5.
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RX630 Group Table 5.18 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (3) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Item Simple SPI SCK clock cycle output (master) Symbol Min. Max. Unit*1 Test Conditions tSPcyc 4 65536 tPcyc Figure 5.
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RX630 Group Table 5.19 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (4) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symb ol Min.*1,*2 Max. Unit Test Conditions tSCL 6(12) × tIICcyc + 1300 — ns Figure 5.
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RX630 Group Table 5.20 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (5) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Symbol Min.*, *2 Max.* Unit SCL input cycle time tSCL 6(12) × tIICcyc + 240 — ns Item RIIC (Fast-mode+) ICFER.
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RX630 Group 5. Electrical Characteristics PCLK Output compare output Input capture input Figure 5.25 tTICW MTU Input/Output Timing PCLK MTCLKA to MTCLKH tTCKWL Figure 5.26 tTCKWH MTU Clock Input Timing PCLK POEn# input tPOEW Figure 5.27 POE# Input Timing PCLK TMCI0 to TMCI3 tTMCWL Figure 5.28 tTMCWH 8-Bit Timer Clock Input Timing R01DS0060EJ0160 Rev.1.
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RX630 Group 5. Electrical Characteristics tSCKW tSCKr tSCKf SCKn (n = 0 to 12) tScyc Figure 5.29 SCK Clock Input Timing SCKn tTXD TxDn tRXS tRXH RxDn n = 0 to 12 Figure 5.30 SCI Input/Output Timing: Clock Synchronous Mode PCLK ADTRG0#-A/B ADTRG1# tTRGW Figure 5.31 A/D Converter External Trigger Input Timing R01DS0060EJ0160 Rev.1.
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RX630 Group 5. Electrical Characteristics RSPI Simple SPI RSPCKm Master select output SCKn Master select output tSPCKr tSPCKWH VOH VOH tSPCKf VOH VOH VOL VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH RSPCKm Slave select input SCKn Slave select input (m = A to C) (n = 0 to 12) VIH VIH VIL tSPCKf VIH VIH VIL tSPCKWL VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 5.
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RX630 Group RSPI 5. Electrical Characteristics Simple SPI tTD SSLm0 to SSLm3 output tLEAD RSPCKm CPOL = 0 output SCKn CKPOL = 1 output RSPCKm CPOL = 1 output SCKn CKPOL = 0 output tLAG tSSLr, tSSLf tSU MISOm input SMISOm input tH MSB IN DATA tOH MOSIm output SMOSIm output (m = A to C) (n = 0 to 12) Figure 5.
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RX630 Group 5. Electrical Characteristics RSPI Simple SPI SSLm0 input SSLn# input RSPCKm CPOL = 0 input SCKn CKPOL = 1 input RSPCKm CPOL = 1 input SCKn CKPOL = 0 input tTD tLEAD tLAG tSA MISOm output SMISOm output tOH tOD LSB OUT (Last data) MSB OUT tSU MOSIm input SMOSIm input (m = A to C) (n = 0 to 12) Figure 5.
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RX630 Group 5.4 5. Electrical Characteristics USB Characteristics Table 5.21 On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 24 to 50 MHz Ta = Topr High drive output is selected by the drive capacity control register. Item Input characteristics Output characteristics Symbol Min. Max. Unit Input high level voltage VIH 2.
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RX630 Group 5.5 5. Electrical Characteristics A/D Conversion Characteristics Table 5.22 10-Bit A/D Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr Item Resolution Conversion time*1 (Operation at PCLK = 50 MHz) enough*2 Min. Typ. Max. Unit 10 3.0 10 10 Bit (2.5)*3 — — µs Test Conditions Sampling in 125 states With 0.
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RX630 Group Table 5.23 5. Electrical Characteristics 12-Bit A/D Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V PCLK = 8 to 50 MHz Ta = Topr Item Resolution Conversion time*1 (Operation at PCLK = 50 MHz) Min. Typ. Max. Unit 12 Test Conditions 12 12 Bit (0.4)*2 — — µs Sampling in 20 states AN0 to AN7 Permissible signal source impedance (max.) = 1.0 kΩ 1.
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RX630 Group 5.6 5. Electrical Characteristics D/A Conversion Characteristics Table 5.25 D/A Conversion Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to VCC VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Min. Typ. Max. Unit Test Conditions Resolution 10 10 10 Bit Conversion time — — 3.0 µs 20-pF capacitive load Absolute accuracy — ±2.0 ±4.0 LSB 2-MΩ resistive load — — ±3.0 LSB 4-MΩ resistive load — — ±2.
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RX630 Group 5.8 5. Electrical Characteristics Power-on Reset Circuit and Voltage Detection Circuit Characteristics Table 5.27 Power-on Reset Circuit and Voltage Detection Circuit Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Voltage detection level Power-on reset (POR) Low power consumption function disabled Symbol Min. Typ. Max. Unit Test Conditions VPOR 2.5 2.6 2.
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RX630 Group 5. Electrical Characteristics tVOFF VCC Vdet0 Internal reset signal (active-low) tdet Figure 5.41 tLVD0 Voltage Detection Circuit Timing (Vdet0) tVOFF VCC VLVH Vdet1 LVD1E Td(E-A) LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal (active-low) When LVD1RN = L tdet tdet tLVD1 When LVD1RN = H tLVD1 Figure 5.42 Voltage Detection Circuit Timing (Vdet1) R01DS0060EJ0160 Rev.1.
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RX630 Group 5. Electrical Characteristics tVOFF VCC VLVH Vdet2 LVD2E Td(E-A) LVD2 Comparator output LVD2CMPE LVD2MON Internal reset signal (active-low) When LVD2RN = L tdet tdet tLVD2 When LVD2RN = H tLVD2 Figure 5.43 Voltage Detection Circuit Timing (Vdet2) R01DS0060EJ0160 Rev.1.
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RX630 Group 5.9 5. Electrical Characteristics Oscillation Stop Detection Timing Table 5.28 Oscillation Stop Detection Circuit Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions Detection time tdr — — 1 ms Figure 5.44 Main clock or PLL clock tdr OSTDSR.OSTDF LOCO clock ICLK Figure 5.
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RX630 Group 5.10 5. Electrical Characteristics Battery Backup Function Characteristics Table 5.29 Battery Backup Function Characteristics Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions V Figure 5.45 Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.
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RX630 Group 5.11 5. Electrical Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.30 ROM (Flash Memory for Code Storage) Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Temperature range for the programming/erasure operation: Ta = Topr Item Symbol Min. Typ. Max.
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RX630 Group 5.12 5. Electrical Characteristics E2 Flash Characteristics Table 5.32 E2 Flash Characteristics (1) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0 VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V Temperature range for the programming/erasure operation: Ta = Topr Item Symbol Min. Typ. Max. Unit Reprogram/erase cycle*1 NDPEC 100000 — — Times Data hold time tDDRP 30*2 — — Year Test Conditions Ta = +85°C Note 1.
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RX630 Group 5. Electrical Characteristics • Suspension during programming FCU command Program Suspend tSPD FSTATR0.FRDY Ready Programming pulse Not Ready Ready Programming • Suspension during erasure in suspend priority mode FCU command Erase Suspend Resume Suspend tSESD1 FSTATR0.FRDY Ready Erasure pulse Not Ready tSESD2 Ready Erasing Not Ready Erasing • Suspension during erasure in erasure priority mode FCU command Erase Suspend tSEED FSTATR0.FRDY Ready Erasure pulse Figure 5.
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RX630 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-TFLGA177-8x8-0.50 RENESAS Code PTLG0177KA-A w S B Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas Electronics Corporation website. D Previous Code 177F0E-A MASS[Typ.] 0.
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RX630 Group Appendix 1. Package Dimensions Figure B 176-Pin LFBGA (PLBG0176GA-A) R01DS0060EJ0160 Rev.1.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP176-24x24-0.50 RENESAS Code PLQP0176KB-A Previous Code 176P6Q-A / FP-176E / FP-176EV MASS[Typ.] 1.8g HD *1 D 132 89 88 133 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA145-7x7-0.50 RENESAS Code PTLG0145KA-A Previous Code 145F0G MASS[Typ.] 0.1g w S B b1 D S AB b S AB w S A ZD A e e N M L K J E H G F E D C B y S x4 v Index mark (Laser mark) ZE A 1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y ZD ZE Nom Max 7.0 7.0 0.15 0.20 1.05 0.5 0.21 0.25 0.29 0.29 0.34 0.39 0.08 0.10 0.5 0.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA100-5.5x5.5-0.50 RENESAS Code PTLG0100KA-A Previous Code 100F0M MASS[Typ.] 0.1g φ b1 φ× M S w S B φb D w S A AB φ× M S ZD A AB e e A K J H G B E F E D C B ZE A ×4 1 v 2 y S Index mark Index mark (Laser mark) S 3 4 5 6 7 8 9 10 Reference Dimension in Millimeters Symbol D E v w A e b b1 x y ZD ZE Min Nom Max 5.5 5.5 0.15 0.20 1.05 0.5 0.21 0.25 0.29 0.29 0.34 0.39 0.08 0.10 0.5 0.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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RX630 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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REVISION HISTORY RX630 Group REVISION HISTORY REVISION HISTORY Rev. 0.50 1.00 Date Page — RX630 Group Datasheet Description Summary May 13, 2011 First Edition issued Sep 13, 2011 All 1. Overview 2, 4, 6 Table 1.1 Outline of Specifications: Reset, real time clock, package, changed 8 to 9 Table 1.3 List of Products Table, changed 12 Table 1.4 List of Pin Functions: BSCANP pin, added 17 Figure 1.3 Pin Assignments (177-Pin TFLGA), added 18 Figure 1.4 Pin Assignments (176-Pin LFBGA), added 19 Figure 1.
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RX630 Group REVISION HISTORY Classifications - Items with Technical Update document number: Changes according to the corresponding issued Technical Update - Items without Technical Update document number: Minor changes that do not require Technical Update to be issued Rev. 1.60 Date Page May 19. 2014 Features 1 Description Summary Operating temp. range, changed Unique ID, added 1. Overview All Name of the on-chip emulator pin, changed: TRSYNC# → TRSYNC 2 to 6 Table 1.
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RX630 Group Rev. 1.60 Date May 19. 2014 2. Page 120 120 121 123 124 125 126 129 129 130 130 131 131 132 133 134 139 140 141 141 142 142 Description Classification Summary Figure 5.21 External Bus Timing/Page Read Cycle (Bus Clock Synchronized), changed Figure 5.22 External Bus Timing/Page Write Cycle (Bus Clock Synchronized), changed Figure 5.23 External Bus Timing/External Wait Control, changed Table 5.17 Timing of On-Chip Peripheral Modules (2), changed Table 5.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual.
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.