Datasheet

R01DS0060EJ0160 Rev.1.60 Page 101 of 154
May 19, 2014
RX630 Group 4. I/O Registers
007F C402h FLASH Flash mode register FMODR 8 8 2, 3 FCLK 2, 3 ICLK Flash Memory
007F C410h FLASH Flash access status register FASTAT 8 8 2, 3 FCLK 2, 3 ICLK
007F C411h FLASH Flash access error interrupt enable register FAEINT 8 8 2, 3 FCLK 2, 3 ICLK
007F C412h FLASH Flash ready interrupt enable register FRDYIE 8 8 2, 3 FCLK 2, 3 ICLK
007F C440h FLASH E2 DataFlash read enable register 0 DFLRE0 16 16 2, 3 FCLK 2, 3 ICLK
007F C442h FLASH E2 DataFlash read enable register 1 DFLRE1 16 16 2, 3 FCLK 2, 3 ICLK
007F C450h FLASH E2 DataFlash P/E enable register 0 DFLWE0 16 16 2, 3 FCLK 2, 3 ICLK
007F C452h FLASH E2 DataFlash P/E enable register 1 DFLWE1 16 16 2, 3 FCLK 2, 3 ICLK
007F C454h FLASH FCU RAM enable register FCURAME 16 16 2, 3 FCLK 2, 3 ICLK
007F FFB0h FLASH Flash status register 0 FSTATR0 8 8 2, 3 FCLK 2, 3 ICLK
007F FFB1h FLASH Flash status register 1 FSTATR1 8 8 2, 3 FCLK 2, 3 ICLK
007F FFB2h FLASH Flash P/E mode entry register FENTRYR 16 16 2, 3 FCLK 2, 3 ICLK
007F FFB4h FLASH Flash protection register FPROTR 16 16 2, 3 FCLK 2, 3 ICLK
007F FFB6h FLASH Flash reset register FRESETR 16 16 2, 3 FCLK 2, 3 ICLK
007F FFBAh FLASH FCU command register FCMDR 16 16 2, 3 FCLK 2, 3 ICLK
007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2, 3 FCLK 2, 3 ICLK
007F FFCAh FLASH E2 data flash blank check control register DFLBCCNT 16 16 2, 3 FCLK 2, 3 ICLK
007F FFCCh FLASH Flash P/E status register FPESTAT 16 16 2, 3 FCLK 2, 3 ICLK
007F FFCEh FLASH E2 DataFlash blank check status register DFLBCSTAT 16 16 2, 3 FCLK 2, 3 ICLK
007F FFE8h FLASH Peripheral clock notification register PCKAR 16 16 2, 3 FCLK 2, 3 ICLK
FEFF FAC0h FLASH Unique ID register 0*
9
UIDR0 8 8 1 ICLK 1 ICLK
FEFF FAC1h FLASH Unique ID register 1*
9
UIDR1 8 8 1 ICLK 1 ICLK
FEFF FAC2h FLASH Unique ID register 2*
9
UIDR2 8 8 1 ICLK 1 ICLK
FEFF FAC3h FLASH Unique ID register 3*
9
UIDR3 8 8 1 ICLK 1 ICLK
FEFF FAC4h FLASH Unique ID register 4*
9
UIDR4 8 8 1 ICLK 1 ICLK
FEFF FAC5h FLASH Unique ID register 5*
9
UIDR5 8 8 1 ICLK 1 ICLK
FEFF FAC6h FLASH Unique ID register 6*
9
UIDR6 8 8 1 ICLK 1 ICLK
FEFF FAC7h FLASH Unique ID register 7*
9
UIDR7 8 8 1 ICLK 1 ICLK
FEFF FAC8h FLASH Unique ID register 8*
9
UIDR8 8 8 1 ICLK 1 ICLK
FEFF FAC9h FLASH Unique ID register 9*
9
UIDR9 8 8 1 ICLK 1 ICLK
FEFF FACAh FLASH Unique ID register 10*
9
UIDR10 8 8 1 ICLK 1 ICLK
FEFF FACBh FLASH Unique ID register 11*
9
UIDR11 8 8 1 ICLK 1 ICLK
FEFF FACCh FLASH Unique ID register 12*
9
UIDR12 8 8 1 ICLK 1 ICLK
FEFF FACDh FLASH Unique ID register 13*
9
UIDR13 8 8 1 ICLK 1 ICLK
FEFF FACEh FLASH Unique ID register 14*
9
UIDR14 8 8 1 ICLK 1 ICLK
FEFF FACFh FLASH Unique ID register 15*
9
UIDR15 8 8 1 ICLK 1 ICLK
FEFF FAD2h TEMPS Temperature sensor calibration data register*
9
TSCDRL 8 8 1 ICLK 1 ICLK Temperature
sensor
FEFF FAD3h TEMPS Temperature sensor calibration data register*
9
TSCDRH 8 8 1 ICLK 1 ICLK
Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively.
Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively.
Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Note 5. Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 26.4 lists
register allocation for 16-bit access in the User’s manual: Hardware.
Note 6. The CAN2 module is not provided in products less than 1 Mbyte of ROM.
Note 7. The CAN0 module is not provided in products less than 512 Kbytes of ROM.
Note 8. When the register is accessed while the USB is operating, a delay may be generated in accessing.
Note 9. These registers are only present in the G version.
Table 4.1 List of I/O Registers (Address Order) (42/42)
Address
Module
Symbol Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
Related
Function ICLK PCLK ICLK  PCLK