Datasheet

R01DS0060EJ0160 Rev.1.60 Page 2 of 154
May 19, 2014
RX630 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Comparison of
Functions for Different Packages.
Table 1.1 Outline of Specifications (1/5)
Classification Module/Function Description
CPU CPU  Maximum operating frequency: 100 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per state (cycle of the system
clock)
 Address space: 4-Gbyte linear
 Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
 Basic instructions: 73
 Floating-point operation instructions: 8
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32 × 32  64 bits
 On-chip divider: 32 / 32  32 bits
 Barrel shifter: 32 bits
 Memory protection unit (MPU)
FPU  Single precision floating point (32 bits)
 Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory ROM  Capacity: 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes
 100 MHz, no-wait access
 On-board programming: Four types
 Off-board programming (parallel programmer mode)
RAM  Capacity: 64 Kbytes, 96 Kbytes, 128 Kbytes
 100 MHz, no-wait access
E
2
data flash  Capacity: 32 Kbytes
 Programming/erasing: 100,000 times
MCU operating modes Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled
extended mode (software switching)
Clock Clock generation circuit  Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and dedicated on-chip oscillator for the IWDT
 Main-clock oscillation stop detection
 Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
Reset RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.