Datasheet

R01DS0060EJ0160 Rev.1.60 Page 110 of 154
May 19, 2014
RX630 Group 5. Electrical Characteristics
5.3.2 Clock Timing
Note 1. This is the time until the clock is used after setting P36 and P37 as inputs, and then clearing the main clock oscillator stop bit
(MOSCCR.MOSTP) to 0 (selecting operation).
Note 2. This is the time until the frequency of oscillation by the HOCO (fHOCO) reaches the range for guaranteed operation. after
release from the reset state.
Note 3. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 4. The number of cycles n selected by the value of the MOSCWTCR.MSTS[4:0] bits determines the main-clock oscillation
stabilization waiting time in accord with the formula below.
Note 5. The number of cycles n selected by the value of the PLLWTCR.PSTS[4:0] bits determines the PLL-clock oscillation stabilization
waiting time in accord with the formula below.
Table 5.11 Clock Timing (Except for Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V
BATT
= 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, T
a
= T
opr
Item Symbol Min. Typ. Max. Unit
Test
Conditions
BCLK pin output cycle time
t
Bcyc
40 — —
ns
Figure 5.3
BCLK pin output high pulse width
t
CH
15 — —
ns
BCLK pin output low pulse width
t
CL
15 — —
ns
BCLK pin output rising time
t
Cr
——5
ns
BCLK pin output falling time
t
Cf
——5
ns
EXTAL external clock input cycle time
t
EXcyc
50 — —
ns
Figure 5.4
EXTAL external clock input high pulse width
t
EXH
20 — —
ns
EXTAL external clock input low pulse width
t
EXL
20 — —
ns
EXTAL external clock rising time
t
EXr
——5
ns
EXTAL external clock falling time
t
EXf
——5
ns
EXTAL external clock input wait time*
1
t
EXWT
1——
ms
Main clock oscillator oscillation frequency
f
MAIN
4—16
MHz
Main clock oscillation stabilization time (crystal)
t
MAINOSC
———*
3
ms
Figure 5.5
Main clock oscillation stabilization wait time (crystal)
t
MAINOSCWT
———*
4
ms
LOCO and IWDTCLK clock cycle time
t
cyc
6.96 8 9.4
µs
LOCO and IWDTCLK clock oscillation frequency
f
LOCO
106.25 125 143.75
kHz
LOCO and IWDTCLK clock oscillation stabilization wait time
t
LOCOWT
——20
µs
Figure 5.6
HOCO clock oscillator oscillation frequency
f
HOCO
45 50 55
MHz
HOCO clock oscillation stabilization wait time 1*
2
t
HOCOWT1
——1.8
ms
Figure 5.7
HOCO clock oscillation stabilization wait time 2
t
HOCOWT2
——2.0
ms
Figure 5.8
HOCO clock power supply settling time
t
HOCOP
——1
ms
Figure 5.9
PLL circuit oscillation frequency
f
PLL
104 — 200
MHz
PLL clock oscillation stabilization time
PLL operation started
after main clock
oscillation has settled
t
PLL1
— — 500
µs
Figure 5.10
PLL clock oscillation stabilization wait t
PLLWT1
———*
5
ms
PLL clock oscillation stabilization time PLL operation started
before main clock
oscillation has settled
t
PLL2
—— t
MAINOSC
+t
PLL1
ms
Figure 5.11
PLL clock oscillation stabilization wait t
PLLWT2
———*
5
ms
t
MAINOSCWT
n +16384
f
MAIN
t
MAINOSC
=
+
t
PLLWT1
n +131072
f
PLL
t
PLL1
=
+
n +131072
f
PLL
=
t
PLLWT2
t
PLL2
+
n +131072
f
PLL
t
MAINOSC
t
PLL1
+
=
+