Datasheet

R01DS0052EJ0140 Rev.1.40 Page 99 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
5.3.3 Bus Timing
Table 5.10
Bus Timing [176-pin LFBGA/145-pin TFLGA/144-pin LQFP]
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
ICLK = 8 to 100 MHz, BCLK = 8 to 100 MHz, SDCLK = 8 to 50 MHz
T
a
= -40 to +85C
Output load conditions: V
OH
= VCC×0.5, V
OL
= VCC×0.5, I
OH
= -1.0 mA, I
OL
= 1.0 mA, C = 30 pF
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
—15ns
Figure 5.10 to Figure 5.13
Byte control delay time t
BCD
—15ns
CS# delay time t
CSD
—15ns
RD# delay time t
RSD
—15ns
Read data setup time t
RDS
15 — ns
Read data hold time t
RDH
0.0 — ns
WR# delay time t
WRD
—15ns
Write data delay time t
WDD
—15ns
Write data hold time t
WDH
0—ns
WAIT# setup time t
WTS
15 — ns
Figure 5.14
WAIT# hold time t
WTH
0.0 — ns
Address delay time 2 (SDRAM) t
AD2
115ns
Figure 5.22 to Figure 5.28
CS# delay time 2 (SDRAM) t
CSD2
115ns
DQM delay time (SDRAM) t
DQMD
115ns
CKE delay time (SDRAM) t
CKED
115ns
Read data setup time 2 (SDRAM) t
RDS2
12 — ns
Read data hold time 2 (SDRAM) t
RDH2
0—ns
Write data delay time 2 (SDRAM) t
WDD2
—15ns
Write data hold time 2 (SDRAM) t
WDH2
1—ns
WE# delay time (SDRAM) t
WED
115ns
RAS# delay time (SDRAM) t
RASD
115ns
CAS# delay time (SDRAM) t
CASD
115ns