Datasheet
R01DS0052EJ0140 Rev.1.40 Page 98 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
5.3.2 Control Signal Timing
Note 1. Both the time and the number of cycles should satisfy the specifications.
Note 2. This is to specify the FCU reset.
Note 3. t
Icyc
: ICLK cycles
Figure 5.7 Reset Input Timing
Figure 5.8 NMI Interrupt Input Timing
Figure 5.9 IRQ Interrupt Input Timing
Table 5.9
Control Signal Timing
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
RES# pulse width
(except for programming or erasure of the ROM or data-flash memory
or blank checking of the data-flash memory)
t
RESW
*1
20 —
t
Icyc
*3
Figure 5.7
1.5 — µs
Internal reset time
*2
t
RESW2
35 — µs
NMI pulse width t
NMIW
200 — ns Figure 5.8
IRQ pulse width t
IRQW
200 — ns Figure 5.9
RES#
t
RESW
NMI
t
NMIW
IRQ
t
IRQW