Datasheet

R01DS0052EJ0140 Rev.1.40 Page 94 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
5.3.1 Clock Timing
Table 5.8
Clock Timing
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
BCLK pin output cycle time
[176-pin LFBGA/145-pin TFLGA/144-pin LQFP]
t
Bcyc
20
125 ns Figure 5.1
BCLK pin output cycle time
[100-pin LQFP/85-pin TFLGA]
t
Bcyc
40
125 ns
BCLK pin output high pulse width t
CH
5
—ns
BCLK pin output low pulse width t
CL
5
—ns
BCLK pin output rising time t
Cr
—
5ns
BCLK pin output falling time t
Cf
—
5ns
SDCLK pin output cycle time t
SDcyc
20
125 ns
SDCLK pin output high pulse width t
CH
5
—ns
SDCLK pin output low pulse width t
CL
5
—ns
SDCLK pin output rising time t
Cr
—
5ns
SDCLK pin output falling time t
Cf
—
5ns
Oscillation settling time after reset (crystal) t
OSC1
10
— ms Figure 5.2
Oscillation settling time after leaving software standby mode
(crystal)
t
OSC2
10
— ms Figure 5.3
Oscillation settling time after leaving deep software standby mode
(crystal)
t
OSC3
10
— ms Figure 5.4
EXTAL external clock output delay settling time t
DEXT
1
— ms Figure 5.2
EXTAL external clock input low pulse width t
EXL
30.71
— ns Figure 5.5
EXTAL external clock input high pulse width t
EXH
30.71
—ns
EXTAL external clock rising time t
EXr
—
5ns
EXTAL external clock falling time t
EXf
—
5ns
XCIN sub-clock oscillation settling time t
SUBOSC
2
— s Figure 5.6
XCIN sub-clock oscillation frequency f
SUB
32.768
—kHz
On-chip oscillator (IWDTCLK) oscillation frequency f
IWDTCLK
62.5
187.5 kHz