Datasheet

R01DS0052EJ0140 Rev.1.40 Page 87 of 150
2014.07.16
RX62N Group, RX621 Group 4. I/O Registers
Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address
is 000881ECh. When different output triggers are specified, the PPG0.NDRH2 addresses for pulse output groups 2 and 3 are
000881EEh and 000881ECh, respectively.
Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is
000881EDh. When different output triggers are specified, the PPG0.NDRL2 addresses for pulse output groups 0 and 1 are
000881EFh and 000881EDh, respectively.
Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address
is 000881FCh. When different output triggers are specified, the PPG1.NDRH2 addresses for pulse output groups 6 and 7 are
000881FEh and 000881FCh, respectively.
Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is
000881FDh. When different output triggers are specified, the PPG1.NDRL2 addresses for pulse output groups 4 and 5 are
000881FFh and 000881FDh, respectively.
Note 5. This register is not supported by the 145-pin TFLGA or 144-pin LQFP version.
Note 6. This register is not supported by the 100-pin LQFP version.
Note 7. This register is not supported by the 85-pin TFLGA version.
Note 8. The number of access states depends on the number of divided cycles for clock synchronization (0 to 1 PCLK, 0 to 1 BCLK).
Note 9. Access may be disabled if a register is accessed during the USB operation.
007F FFB1h FLASH Flash status register 1 FSTATR1 8 8 2 to 3 PCLK*
8
007F FFB2h FLASH Flash P/E mode entry register FENTRYR 16 16 2 to 3 PCLK*
8
007F FFB4h FLASH Flash protect register FPROTR 16 16 2 to 3 PCLK*
8
007F FFB6h FLASH Flash reset register FRESETR 16 16 2 to 3 PCLK*
8
007F FFBAh FLASH FCU command register FCMDR 16 16 2 to 3 PCLK*
8
007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2 to 3 PCLK*
8
007F FFCAh FLASH Data flash blank check control register DFLBCCNT 16 16 2 to 3 PCLK*
8
007F FFCCh FLASH Flash P/E status register FPESTAT 16 16 2 to 3 PCLK*
8
007F FFCEh FLASH Data flash blank check status register DFLBCSTAT 16 16 2 to 3 PCLK*
8
007F FFE8h FLASH Peripheral clock notification register PCKAR 16 16 2 to 3 PCLK*
8
Table 4.1 List of I/O Registers (Address Order) (36 / 36)
Address
Module
Abbreviation Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access Cycles