Datasheet
R01DS0052EJ0140 Rev.1.40 Page 85 of 150
2014.07.16
RX62N Group, RX621 Group 4. I/O Registers
000A 029Ch USB1 Pipe 4 transaction counter enable
register
PIPE4TRE 16 16 at least 9
PCLK*
9
000A 029Eh USB1 Pipe 4 transaction counter register PIPE4TRN 16 16 at least 9
PCLK*
9
000A 02A0h USB1 Pipe 5 transaction counter enable
register
PIPE5TRE 16 16 at least 9
PCLK*
9
000A 02A2h USB1 Pipe 5 transaction counter register PIPE5TRN 16 16 at least 9
PCLK*
9
000A 02D0h USB1 Device address 0 configuration register DEVADD0 16 16 at least 9
PCLK*
9
000A 02D2h USB1 Device address 1 configuration register DEVADD1 16 16 at least 9
PCLK*
9
000A 02D4h USB1 Device address 2 configuration register DEVADD2 16 16 at least 9
PCLK*
9
000A 02D6h USB1 Device address 3 configuration register DEVADD3 16 16 at least 9
PCLK*
9
000A 02D8h USB1 Device address 4 configuration register DEVADD4 16 16 at least 9
PCLK*
9
000A 02DAh USB1 Device address 5 configuration register DEVADD5 16 16 at least 9
PCLK*
9
000A 0400h USB Deep standby USB transceiver control/
pin monitor register
DPUSR0R 32 32 1 to 2PCLK*
8
000A 0404h USB Deep standby USB suspend/resume
interrupt register
DPUSR1R 32 32 1 to 2PCLK*
8
000C 0000h EDMAC EDMAC mode register EDMR 32 32 4 to 5 ICLK
000C 0008h EDMAC EDMAC transmit request register EDTRR 32 32 4 to 5 ICLK
000C 0010h EDMAC EDMAC receive request register EDRRR 32 32 4 to 5 ICLK
000C 0018h EDMAC Transmit descriptor list start address
register
TDLAR 32 32 4 to 5 ICLK
000C 0020h EDMAC Receive descriptor list start address
register
RDLAR 32 32 4 to 5 ICLK
000C 0028h EDMAC ETHERC/EDMAC status register EESR 32 32 4 to 5 ICLK
000C 0030h EDMAC ETHERC/EDMAC status interrupt
permission register
EESIPR 32 32 4 to 5 ICLK
000C 0038h EDMAC Transmit/receive status copy enable
register
TRSCER 32 32 4 to 5 ICLK
000C 0040h EDMAC Receive missed-frame counter register RMFCR 32 32 4 to 5 ICLK
000C 0048h EDMAC Transmit FIFO threshold register TFTR 32 32 4 to 5 ICLK
000C 0050h EDMAC FIFO depth register FDR 32 32 4 to 5 ICLK
000C 0058h EDMAC Receiving method control register RMCR 32 32 4 to 5 ICLK
000C 0064h EDMAC Transmit FIFO underrun counter TFUCR 32 32 4 to 5 ICLK
000C 0068h EDMAC Receive FIFO overflow counter RFOCR 32 32 4 to 5 ICLK
000C 006Ch EDMAC Independent output signal setting
register
IOSR 32 32 4 to 5 ICLK
000C 0070h EDMAC Flow control start FIFO threshold setting
register
FCFTR 32 32 4 to 5 ICLK
000C 0078h EDMAC Receive data padding insert register RPADIR 32 32 4 to 5 ICLK
000C 007Ch EDMAC Transmit interrupt setting register TRIMD 32 32 4 to 5 ICLK
000C 00C8h EDMAC Receive buffer write address register RBWAR 32 32 4 to 5 ICLK
000C 00CCh EDMAC Receive descriptor fetch address register RDFAR 32 32 4 to 5 ICLK
Table 4.1 List of I/O Registers (Address Order) (34 / 36)
Address
Module
Abbreviation Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access Cycles