Datasheet
R01DS0052EJ0140 Rev.1.40 Page 82 of 150
2014.07.16
RX62N Group, RX621 Group 4. I/O Registers
000A 0060h USB0 DCP control register DCPCTR 16 16 at least 9
PCLK*
9
000A 0064h USB0 Pipe window select register PIPESEL 16 16 at least 9
PCLK*
9
000A 0068h USB0 Pipe configuration register PIPECFG 16 16 at least 9
PCLK*
9
000A 006Ch USB0 Pipe maximum packet size register PIPEMAXP 16 16 at least 9
PCLK*
9
000A 006Eh USB0 Pipe cycle control register PIPEPERI 16 16 at least 9
PCLK*
9
000A 0070h USB0 Pipe 1 control register PIPE1CTR 16 16 at least 9
PCLK*
9
000A 0072h USB0 Pipe 2 control register PIPE2CTR 16 16 at least 9
PCLK*
9
000A 0074h USB0 Pipe 3 control register PIPE3CTR 16 16 at least 9
PCLK*
9
000A 0076h USB0 Pipe 4 control register PIPE4CTR 16 16 at least 9
PCLK*
9
000A 0078h USB0 Pipe 5 control register PIPE5CTR 16 16 at least 9
PCLK*
9
000A 007Ah USB0 Pipe 6 control register PIPE6CTR 16 16 at least 9
PCLK*
9
000A 007Ch USB0 Pipe 7 control register PIPE7CTR 16 16 at least 9
PCLK*
9
000A 007Eh USB0 Pipe 8 control register PIPE8CTR 16 16 at least 9
PCLK*
9
000A 0080h USB0 Pipe 9 control register PIPE9CTR 16 16 at least 9
PCLK*
9
000A 0090h USB0 Pipe 1 transaction counter enable
register
PIPE1TRE 16 16 at least 9
PCLK*
9
000A 0092h USB0 Pipe 1 transaction counter register PIPE1TRN 16 16 at least 9
PCLK*
9
000A 0094h USB0 Pipe 2 transaction counter enable
register
PIPE2TRE 16 16 at least 9
PCLK*
9
000A 0096h USB0 Pipe 2 transaction counter register PIPE2TRN 16 16 at least 9
PCLK*
9
000A 0098h USB0 Pipe 3 transaction counter enable
register
PIPE3TRE 16 16 at least 9
PCLK*
9
000A 009Ah USB0 Pipe 3 transaction counter register PIPE3TRN 16 16 at least 9
PCLK*
9
000A 009Ch USB0 Pipe 4 transaction counter enable
register
PIPE4TRE 16 16 at least 9
PCLK*
9
000A 009Eh USB0 Pipe 4 transaction counter register PIPE4TRN 16 16 at least 9
PCLK*
9
000A 00A0h USB0 Pipe 5 transaction counter enable
register
PIPE5TRE 16 16 at least 9
PCLK*
9
000A 00A2h USB0 Pipe 5 transaction counter register PIPE5TRN 16 16 at least 9
PCLK*
9
000A 00D0h USB0 Device address 0 configuration register DEVADD0 16 16 at least 9
PCLK*
9
000A 00D2h USB0 Device address 1 configuration register DEVADD1 16 16 at least 9
PCLK*
9
Table 4.1 List of I/O Registers (Address Order) (31 / 36)
Address
Module
Abbreviation Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access Cycles