Datasheet

R01DS0052EJ0140 Rev.1.40 Page 80 of 150
2014.07.16
RX62N Group, RX621 Group 4. I/O Registers
0008 C412h RTC Minute alarm register RMINAR 8 8 2 to 3 PCLK*
8
0008 C414h RTC Hour alarm register RHRAR 8 8 2 to 3 PCLK*
8
0008 C416h RTC Day-of-week alarm register RWKAR 8 8 2 to 3 PCLK*
8
0008 C418h RTC Date alarm register RDAYAR 8 8 2 to 3 PCLK*
8
0008 C41Ah RTC Month alarm register RMONAR 8 8 2 to 3 PCLK*
8
0008 C41Ch RTC Year alarm register RYRAR 16 16 2 to 3 PCLK*
8
0008 C41Eh RTC Year alarm enable register RYRAREN 8 8 2 to 3 PCLK*
8
0008 C422h RTC RTC control register 1 RCR1 8 8 2 to 3 PCLK*
8
0008 C424h RTC RTC control register 2 RCR2 8 8 2 to 3 PCLK*
8
0009 0200h to
0009 03FFh
CAN0 Mailbox registers 0 to 31 MB0 to MB31 128 8, 16, 32 2 to 3 PCLK*
8
0009 0400h CAN0 Mask register 0 MKR0 32 8, 16, 32 2 to 3 PCLK*
8
0009 0404h CAN0 Mask register 1 MKR1 32 8, 16, 32 2 to 3 PCLK*
8
0009 0408h CAN0 Mask register 2 MKR2 32 8, 16, 32 2 to 3 PCLK*
8
0009 040Ch CAN0 Mask register 3 MKR3 32 8, 16, 32 2 to 3 PCLK*
8
0009 0410h CAN0 Mask register 4 MKR4 32 8, 16, 32 2 to 3 PCLK*
8
0009 0414h CAN0 Mask register 5 MKR5 32 8, 16, 32 2 to 3 PCLK*
8
0009 0418h CAN0 Mask register 6 MKR6 32 8, 16, 32 2 to 3 PCLK*
8
0009 041Ch CAN0 Mask register 7 MKR7 32 8, 16, 32 2 to 3 PCLK*
8
0009 0420h CAN0 FIFO received ID compare register 0 FIDCR0 32 8, 16, 32 2 to 3 PCLK*
8
0009 0424h CAN0 FIFO received ID compare register 1 FIDCR1 32 8, 16, 32 2 to 3 PCLK*
8
0009 0428h CAN0 Mask invalid register MKIVLR 32 8, 16, 32 2 to 3 PCLK*
8
0009 042Ch CAN0 Mailbox interrupt enable register MIER 32 8, 16, 32 2 to 3 PCLK*
8
0009 0820h to
0009 083Fh
CAN0 Message control registers 0 to 31 MCTL0 to
MCTL31
8 8 2 to 3 PCLK*
8
0009 0840h CAN0 Control register CTLR 16 8, 16 2 to 3 PCLK*
8
0009 0842h CAN0 Status register STR 16 8, 16 2 to 3 PCLK*
8
0009 0844h CAN0 Bit configuration register BCR 32 8, 16, 32 2 to 3 PCLK*
8
0009 0848h CAN0 Receive FIFO control register RFCR 8 8 2 to 3 PCLK*
8
0009 0849h CAN0 Receive FIFO pointer control register RFPCR 8 8 2 to 3 PCLK*
8
0009 084Ah CAN0 Transmit FIFO control register TFCR 8 8 2 to 3 PCLK*
8
0009 084Bh CAN0 Transmit FIFO pointer control register TFPCR 8 8 2 to 3 PCLK*
8
0009 084Ch CAN0 Error interrupt enable register EIER 8 8 2 to 3 PCLK*
8
0009 084Dh CAN0 Error interrupt factor judge register EIFR 8 8 2 to 3 PCLK*
8
0009 084Eh CAN0 Receive error count register RECR 8 8 2 to 3 PCLK*
8
0009 084Fh CAN0 Transmit error count register TECR 8 8 2 to 3 PCLK*
8
0009 0850h CAN0 Error code store register ECSR 8 8 2 to 3 PCLK*
8
0009 0851h CAN0 Channel search support register CSSR 8 8 2 to 3 PCLK*
8
0009 0852h CAN0 Mailbox search status register MSSR 8 8 2 to 3 PCLK*
8
0009 0853h CAN0 Mailbox search mode register MSMR 8 8 2 to 3 PCLK*
8
0009 0854h CAN0 Time stamp register TSR 16 8, 16 2 to 3 PCLK*
8
0009 0856h CAN0 Acceptance filter support register AFSR 16 8, 16 2 to 3 PCLK*
8
0009 0858h CAN0 Test control register TCR 8 8 2 to 3 PCLK*
8
000A 0000h USB0 System configuration control register SYSCFG 16 16 3 to 4 PCLK*
8
000A 0004h USB0 System configuration status register 0 SYSSTS0 16 16 at least 9
PCLK*
9
Table 4.1 List of I/O Registers (Address Order) (29 / 36)
Address
Module
Abbreviation Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access Cycles