Datasheet

R01DS0052EJ0140 Rev.1.40 Page 54 of 150
2014.07.16
RX62N Group, RX621 Group 4. I/O Registers
0008 284Ch EXDMAC1 EXDMA block transfer count register EDMCRB 16 16 1 to 2 BCLK*
8
0008 2850h EXDMAC1 EXDMA transfer mode register EDMTMD 16 16 1 to 2 BCLK*
8
0008 2852h EXDMAC1 EXDMA output setting register EDMOMD 8 8 1 to 2 BCLK*
8
0008 2853h EXDMAC1 EXDMA interrupt setting register EDMINT 8 8 1 to 2 BCLK*
8
0008 2854h EXDMAC1 EXDMA address mode register EDMAMD 32 32 1 to 2 BCLK*
8
0008 285Ch EXDMAC1 EXDMA transfer enable register EDMCNT 8 8 1 to 2 BCLK*
8
0008 285Dh EXDMAC1 EXDMA software start register EDMREQ 8 8 1 to 2 BCLK*
8
0008 285Eh EXDMAC1 EXDMA status register EDMSTS 8 8 1 to 2 BCLK*
8
0008 2860h EXDMAC1 EXDMA external request sense mode
register
EDMRMD 8 8 1 to 2 BCLK*
8
0008 2861h EXDMAC1 EXDMA external request flag register EDMERF 8 8 1 to 2 BCLK*
8
0008 2862h EXDMAC1 EXDMA peripheral request flag register EDMPRF 8 8 1 to 2 BCLK*
8
0008 2A00h EXDMAC EXDMA module start register EDMAST 8 8 1 to 2 BCLK*
8
0008 2BE0h EXDMAC Cluster buffer register 0 CLSBR0 32 32 1 to 2 BCLK*
8
0008 2BE4h EXDMAC Cluster buffer register 1 CLSBR1 32 32 1 to 2 BCLK*
8
0008 2BE8h EXDMAC Cluster buffer register 2 CLSBR2 32 32 1 to 2 BCLK*
8
0008 2BECh EXDMAC Cluster buffer register 3 CLSBR3 32 32 1 to 2 BCLK*
8
0008 2BF0h EXDMAC Cluster buffer register 4 CLSBR4 32 32 1 to 2 BCLK*
8
0008 2BF4h EXDMAC Cluster buffer register 5 CLSBR5 32 32 1 to 2 BCLK*
8
0008 2BF8h EXDMAC Cluster buffer register 6 CLSBR6 32 32 1 to 2 BCLK*
8
0008 3002h BSC CS0 mode register CS0MOD 16 16 1 to 2 BCLK*
8
0008 3004h BSC CS0 wait control register 1 CS0WCR1 32 32 1 to 2 BCLK*
8
0008 3008h BSC CS0 wait control register 2 CS0WCR2 32 32 1 to 2 BCLK*
8
0008 3012h BSC CS1 mode register CS1MOD 16 16 1 to 2 BCLK*
8
0008 3014h BSC CS1 wait control register 1 CS1WCR1 32 32 1 to 2 BCLK*
8
0008 3018h BSC CS1 wait control register 2 CS1WCR2 32 32 1 to 2 BCLK*
8
0008 3022h BSC CS2 mode register CS2MOD 16 16 1 to 2 BCLK*
8
0008 3024h BSC CS2 wait control register 1 CS2WCR1 32 32 1 to 2 BCLK*
8
0008 3028h BSC CS2 wait control register 2 CS2WCR2 32 32 1 to 2 BCLK*
8
0008 3032h BSC CS3 mode register CS3MOD 16 16 1 to 2 BCLK*
8
0008 3034h BSC CS3 wait control register 1 CS3WCR1 32 32 1 to 2 BCLK*
8
0008 3038h BSC CS3 wait control register 2 CS3WCR2 32 32 1 to 2 BCLK*
8
0008 3042h BSC CS4 mode register CS4MOD 16 16 1 to 2 BCLK*
8
0008 3044h BSC CS4 wait control register 1 CS4WCR1 32 32 1 to 2 BCLK*
8
0008 3048h BSC CS4 wait control register 2 CS4WCR2 32 32 1 to 2 BCLK*
8
0008 3052h BSC CS5 mode register CS5MOD 16 16 1 to 2 BCLK*
8
0008 3054h BSC CS5 wait control register 1 CS5WCR1 32 32 1 to 2 BCLK*
8
0008 3058h BSC CS5 wait control register 2 CS5WCR2 32 32 1 to 2 BCLK*
8
0008 3062h BSC CS6 mode register CS6MOD 16 16 1 to 2 BCLK*
8
0008 3064h BSC CS6 wait control register 1 CS6WCR1 32 32 1 to 2 BCLK*
8
0008 3068h BSC CS6 wait control register 2 CS6WCR2 32 32 1 to 2 BCLK*
8
0008 3072h BSC CS7 mode register CS7MOD 16 16 1 to 2 BCLK*
8
0008 3074h BSC CS7 wait control register 1 CS7WCR1 32 32 1 to 2 BCLK*
8
0008 3078h BSC CS7 wait control register 2 CS7WCR2 32 32 1 to 2 BCLK*
8
0008 3802h BSC CS0 control register CS0CR 16 16 1 to 2 BCLK*
8
Table 4.1 List of I/O Registers (Address Order) (3 / 36)
Address
Module
Abbreviation Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access Cycles