Datasheet

R01DS0052EJ0140 Rev.1.40 Page 44 of 150
2014.07.16
RX62N Group, RX621 Group 1. Overview
Ethernet controller REF50CK Input 50-MHz reference clock. This pin inputs reference signals for
transmission/reception timings in RMII mode.
RMII_CRS_DV Input Indicates that there are carrier detection signals and valid
receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.
RMII_TXD0, RMII_TXD1 Output 2-bit transmit data in RMII mode.
RMII_RXD0, RMII_RXD1 Input 2-bit receive data in RMII mode.
RMII_TXD_EN Output Output pin for data transmit enable signals in RMII mode.
RMII_RX_ER Input Indicates an error has occurred during reception of data in RMII
mode.
ET_CRS Input Carrier detection/data reception enable pin.
ET_RX_DV Input Indicates that there are valid receive data on ET_ERXD3 to
ET_ERXD0.
ET_EXOUT Output General-purpose external output pin.
ET_LINKSTA Input Inputs link status from the PHY-LSI.
ET_ETXD0 to ET_ETXD3 Output 4 bits of MII transmit data.
ET_ERXD0 to ET_ERXD3 Input 4 bits of MII receive data.
ET_TX_EN Output Transmit enable pin. Indicates that transmit data is ready on
ET_ETXD3 to ET_ETXD0.
ET_TX_ER Output Transmit error pin. Notifies the PHY_LSI of an error during
transmission.
ET_RX_ER Input Receive error pin. Recognizes an error during reception.
ET_TX_CLK Input Transmit clock pin. This pin inputs reference signals for output
timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and
ET_TX_ER.
ET_RX_CLK Input Receive clock pin. This pin inputs reference signals for input
timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and
ET_RX_ER.
ET_COL Input Inputs collision detection signals.
ET_WOL Output Receives Magic Packets
TM
ET_MDC Output Outputs reference clock signals for information transfer via
ET_MDIO.
ET_MDIO I/O These pins carry bidirectional signals for the exchange of
management information between the RX62N Group and the
PHY-LSI.
Table 1.9 Pin Functions (5 / 7)
Classifications Pin Name I/O Description