Datasheet

R01DS0052EJ0140 Rev.1.40 Page 147 of 150
2014.07.16
RX62N Group, RX621 Group REVISION HISTORY
REVISION HISTORY RX62N Group, RX621 Group Datasheet
Rev. Date
Description
Page Summary
1.00 2011.02.04
—
First Edition issued
1.10 2011.02.10
—
Features reviewed
1.20 2011.06.10
1. Overview
2 to 5 Table 1.1 Outline of Specification, Description changed
40 to 46 Table 1.9 Pin Functions, Description changed
4. I/O Registers
52 to 86 Table 4.1 List of I/O Registers (Address Order), Description changed
5. Electrical Characteristics
90 Table 5.2 DC Characteristics (3) , changed
111 Figure 5.23 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area), changed
111 Figure 5.24 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM), changed
1.30 2012.01.11
1. Overview
2 Table 1.1 Outline of Specifications (1/4), changed, note 1, note 2 deleted
13 Figure 1.6 Pin Assignment of the 144-Pin LQFP (Assistance Diagram), changed
15 Figure 1.8 Pin Assignment of the 100-Pin LQFP (Assistance Diagram), changed
33 Table 1.7 List of Pins and Pin Functions (100-Pin LQFP) (1/4), changed
37 Table 1.8 List of Pins and Pin Functions (85-Pin TFLGA) (2/3), changed
4. I/O Registers
52 to 87 Table 4.1 List of I/O Registers (Address Order), Description changed
5. Electrical Characteristics
91 Table 5.4 DC Characteristics (3), specification added
98 Table 5.9 Control Signal Timing, note changed
122 Table 5.18 Timing of On-Chip Peripheral Modules (6), conditions changed
REVISION HISTORY