Datasheet

R01DS0052EJ0140 Rev.1.40 Page 122 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Figure 5.25 I/O Port Input/Output Timing
Figure 5.26 MTU2 Input/Output Timing
Table 5.18
Timing of On-Chip Peripheral Modules (10)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Typ. Max. Unit Test Conditions
TCK clock cycle time t
TCKcyc
100 — — ns Figure 5.58
TCK clock high pulse width t
TCKH
45——ns
TCK clock low pulse width t
TCKL
45——ns
TCK clock rising time t
TCKr
——5 ns
TCK clock falling time t
TCKf
——5 ns
TRST# pulse width t
TRSTW
20——t
TCKcyc
Figure 5.59
TMS setup time t
TMSS
20 — — ns Figure 5.60
TMS hold time t
TMSH
20——ns
TDI setup time t
TDIS
20——ns
TDI hold time t
TDIH
20——ns
TDO data delay time t
TDOD
— — 40 ns
PCLK
T1
t
PRS
T2
t
PRH
t
PWD
Input port (read)
Output port (write)
Output
compare output
Input capture
input
PCLK
t
TOCD
t
TICS
t
TICW