Datasheet

R01DS0052EJ0140 Rev.1.40 Page 121 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0
Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER
Note 3. The user program must make settings so that this stipulation is satisfied.
Table 5.17
Timing of On-Chip Peripheral Modules (9)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
ICLK = 12.5 to 100 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
ETHERC(MII) ET_TX_CLK cycle time t
Tcyc
40 — ns
—
ET_TX_EN output delay time t
TENd
120ns
Figure 5.51
ET_ETXD0 to ET_ETXD3 output delay time t
MTDd
120ns
ET_CRS setup time t
CRSs
10 — ns
ET_CRS hold time t
CRSh
10 — ns
ET_COL setup time t
COLs
10 — ns
Figure 5.52
ET_COL hold time t
COLh
10 — ns
ET_RX_CLK cycle time t
TRcyc
40 — ns
—
ET_RX_DV setup time t
RDVs
10 ns
Figure 5.53
ET_RX_DV hold time t
RDVh
10 — ns
ET_ERXD0 to ET_ERXD3 setup time t
MRDs
10 — ns
ET_ERXD0 to ET_ERXD3 hold time t
MRDh
10 — ns
ET_RX_ER setup time t
RERs
10 — ns
Figure 5.54
ET_RX_ER hold time t
RESh
10 — ns
ET_MDIO setup time t
MDIOs
10 — ns
Figure 5.55
ET_MDIO hold time t
MDIOh
10 — ns
ET_MDIO utput hold time t
MDIOdh
5—ns
Figure 5.56
ET_WOL output delay time t
WOLd
120ns
Figure 5.57