Datasheet

R01DS0052EJ0140 Rev.1.40 Page 119 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Note: t
IICcyc
: RIIC internal reference clock (IICφ) cycles
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. C
b
indicates the total capacity of the bus line.
Table 5.16
Timing of On-Chip Peripheral Modules (7)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol
Min.
*1*2
Max. Unit
Test Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time t
SCL
6(12) × t
IICcyc
+ 240 —
ns Figure 5.43
SCL input high pulse width t
SCLH
3(6) × t
IICcyc
+ 120 —
ns
SCL input low pulse width t
SCLL
3(6) × t
IICcyc
+ 120 —
ns
SCL, SDA input rising time t
Sr
— 120
ns
SCL, SDA input falling time t
Sf
— 120
ns
SCL, SDA input spike pulse removal time t
SP
0 1(4) × t
IICcyc
ns
SDA input bus free time t
BUF
3(6) × t
IICcyc
+ 120 —
ns
Start condition input hold time t
STAH
t
IICcyc
+ 120
ns
Re-start condition input setup time t
STAS
120 —
ns
Stop condition input setup time t
STOS
120 —
ns
Data input setup time t
SDAS
t
IICcyc
+ 20 —
ns
Data input hold time t
SDAH
0—ns
SCL, SDA capacitive load C
b
— 550 pF