Datasheet

R01DS0052EJ0140 Rev.1.40 Page 117 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Table 5.15
Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
RSPI Data output hold time Master t
OH
0 — ns Figure 5.39 to Figure
5.42
Slave 0 —
Successive transmission
delay time
Master t
TD
t
SPcyc
+2 × t
Pcyc
8 × t
SPcyc
+2 × t
Pcyc
ns
Slave 4 × t
Pcyc
—
MOSI, MISO rise/fall time Output
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
t
Dr,
t
Df
—5ns
Output
[100-pin LQFP/
85-pin TFLGA]
—10
Input — 1 µs
SSL rise/fall time Output
[176-pin LFBGA
145-pin TFLGA
144-pin LQFP]
t
SSLr,
t
SSLf
—5ns
Output
[100-pin LQFP/
85-pin TFLGA]
—10
Input — 1 µs
Slave access time t
SA
—4t
Pcyc
Figure 5.41 and Figure
5.42
Slave output release time t
REL
—3t
Pcyc