Datasheet

R01DS0052EJ0140 Rev.1.40 Page 116 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Table 5.14
Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
RSPI Data input setup time Master
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
t
SU
16 — ns Figure 5.39 to
Figure 5.42
Master
[100-pin LQFP/
85-pin TFLGA]
30 —
Slave 20-2 × t
Pcyc
—
Data input hold time Master t
H
0—ns
Slave 20+2 × t
Pcyc
—
SSL setup time Master t
LEAD
18t
SPcyc
Slave 4 — t
Pcyc
SSL hold time Master t
LAG
18t
SPcyc
Slave 4 — t
Pcyc
Data output delay time Master
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
t
OD
—20ns
Master
[100-pin LQFP/
85-pin TFLGA]
—30
Slave
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
—3 × t
Pcyc
+40
Slave
[100-pin LQFP/
85-pin TFLGA]
—3 × t
Pcyc
+50