Datasheet

R01DS0052EJ0140 Rev.1.40 Page 115 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Note 1. tPcyc: PCLK cycle
Table 5.14
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
CAN Transmit data delay time t
CTXD
— 40.0
ns Figure 5.37
Receive data setup time t
CRXS
40.0 —
ns
Receive data hold time t
CRXH
40.0 —
ns
RSPI RSPCK clock cycle Master t
SPcyc
2 4096
t
Pcyc
*1
Figure 5.38
Slave
8 4096
RSPCK clock
high pulse width
Master t
SPCKWH
(t
SPcyc
-t
SPCKR
-t
SPCKF
) / 2-3 —
ns
Slave
(t
SPcyc
-t
SPCKR
-t
SPCKF
) / 2 —
RSPCK clock
low pulse width
Master t
SPCKWL
(t
SPcyc
-t
SPCKR
-t
SPCKF
) / 2-3 —
ns
Slave
(t
SPcyc
-t
SPCKR
-t
SPCKF
) / 2 —
RSPCK clock
rise/fall time
Output
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
t
SPCKr,
t
SPCKf
—5
ns
Output
[100-pin LQFP/
85-pin TFLGA]
—10
Input
—1
µs