Datasheet

R01DS0052EJ0140 Rev.1.40 Page 114 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Table 5.13
Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
SCI Input clock cycle Asynchronous t
Scyc
4 × t
Pcyc
—ns
Figure 5.34 and
Figure 5.35
Clock
synchronous
6 × t
Pcyc
—
Input clock pulse width t
SCKW
0.4 × t
Scyc
0.6 × t
Scyc
ns
Input clock rise time t
SCKr
—20ns
Input clock fall time t
SCKf
—20ns
Output clock cycle Asynchronous t
Scyc
16 × t
Pcyc
—ns
Clock
synchronous
4 × t
Pcyc
—
Output clock pulse width t
SCKW
0.4 × t
Scyc
0.6 × t
Scyc
ns
Output clock rise time t
SCKr
—20ns
Output clock fall time t
SCKf
—20ns
Transmit data delay time
(clock synchronous)
t
TXD
—
40 ns
Receive data setup time
(clock synchronous)
t
RXS
40
—ns
Receive data hold time
(clock synchronous)
t
RXH
40
—ns
A/D
converter
10-bit A/D converter
trigger input setup time
t
TRGS
25
— ns Figure 5.36
12-bit A/D converter
trigger input setup time
t
TRGS
25
—ns