Datasheet

R01DS0052EJ0140 Rev.1.40 Page 113 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
5.3.5 Timing of On-Chip Peripheral Modules
Table 5.13
Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol
Min.
Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
— 40 ns Figure 5.25
Input data setup time t
PRS
25 — ns
Input data hold time t
PRH
25 — ns
MTU2 Output compare output delay time t
TOCD
—40ns
Figure 5.26
Input capture input setup time t
TICS
20 — ns
Input capture input pulse width
(single-edge setting)
t
TICW
1.5 × t
Pcyc
—ns
Input capture input pulse width
(both-edge setting)
t
TICW
2.5 × t
Pcyc
—ns
Timer input setup time t
TCKS
20 — ns
Figure 5.27
Timer clock pulse width
(single-edge setting)
t
TCKWH/L
1.5 × t
Pcyc
—ns
Timer clock pulse width
(both-edge setting)
t
TCKWH/L
2.5 × t
Pcyc
—ns
Timer clock pulse width
(phase counting mode)
t
TCKWH/L
2.5 × t
Pcyc
—ns
POE2 POE# input setup time t
POES
50 — ns
Figure 5.28
POE# input pulse width t
POEW
1.5 × t
Pcyc
—ns
PPG Pulse output delay time t
POD
—40ns
Figure 5.29
8-bit timer Timer output delay time t
TMOD
—40ns
Figure 5.30
Timer reset input setup time t
TMRS
25 — ns
Figure 5.31
Timer clock input setup time t
TMCS
25 — ns
Figure 5.32
Timer clock
pulse width
Single-edge setting t
TMCWH
1.5 × t
Pcyc
—ns
Both-edge setting t
TMCWL
2.5 × t
Pcyc
—ns
WDT Overflow output delay time t
WOVD
—40ns
Figure 5.33