Datasheet

R01DS0052EJ0140 Rev.1.40 Page 112 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
5.3.4 EXDMAC Timing
Figure 5.22 EDREQ0 and EDREQ1 Input Timing
Figure 5.23 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
Figure 5.24 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
Table 5.12
EXDMAC Timing
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz, BCLK = 8 to 100 MHz, SDCLK = 8 to 50 MHz
T
a
= -40 to +85C
Item Symbol Min. Max. Unit Test Conditions
EXDMAC EDREQ setup time t
EDRQS
20 — ns Figure 5.22
EDREQ hold time t
EDRQH
5— ns
EDACK delay time t
EDACD
— 15 ns Figure 5.23 and Figure 5.24
BCLK
t
EDRQS
t
EDRQH
EDREQ0
EDREQ1
EDACK0
EDACK1
t
EDACD
BCLK
t
EDACD
t
EDACD
BCLK
t
EDACD
EDACK0
EDACK1