Datasheet

R01DS0052EJ0140 Rev.1.40 Page 100 of 150
2014.07.16
RX62N Group, RX621 Group 5. Electrical Characteristics
Table 5.11
Bus Timing [100-pin LQFP/85-pin TFLGA]
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0 V
ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz, BCLK = 8 to 50 MHz
T
a
= -40 to +85C
Output load conditions: V
OH
= VCC × 0.5, V
OL
= VCC × 0.5, I
OH
= -1.0 mA, I
OL
= 1.0 mA, C = 30 pF
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
— 30 ns Figure 5.10 to Figure 5.13
Byte control delay time t
BCD
—30 ns
CS# delay time t
CSD
—30 ns
RD# delay time t
RSD
—30 ns
Read data setup time t
RDS
15 — ns
Read data hold time t
RDH
0.0 — ns
WR# delay time t
WRD
—30 ns
Write data delay time t
WDD
—35 ns
Write data hold time t
WDH
0— ns
WAIT# setup time t
WTS
15 — ns Figure 5.14
WAIT# hold time t
WTH
0.0 — ns