Datasheet

R01DS0052EJ0140 Rev.1.40 Page 1 of 150
2014.07.16
DatasheetDatasheet
RX62N Group, RX621 Group
Renesas MCUs
Features
■ 32-bit RX CPU Core
 Delivers 165 DMIPS at a maximum operating frequency of
100 MHz
 Single Precision 32-bit IEEE-754 Floating Point
 Accumulator: 32 × 32 to 64-bit result, one instruction
 Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for
multiple instructions
 Interrupt response in as few as 5 CPU clock cycles
 CISC-Harvard Architecture with 5-stage pipeline
 Variable length instructions, ultra compact code
 Supports the Memory Protection Unit (MPU)
 Background JTAG debug plus high-speed trace
■ Low Power Design and Architecture
 2.7V to 3.6V operation from a single supply
 480 µA/MHz Run Mode with all peripherals on
 Deep Software Standby Mode with RTC
 Four low power modes
■ Main Flash Memory, no Wait-State
 100 MHz operation, 10 nsec read cycle
 No wait states for read at full CPU speed
 256K, 384K, 512K Byte size options
 For Instructions or Operands
 Programming from USB, SCI, JTAG, user code
■ Data Flash Memory
 Up to 32K Bytes with 30K Erase Cycles
 Background Erase/Program does not stall CPU
■ SRAM, no Wait-State
 64K or 96K Byte size options
 For Operands or Instructions
 Back-up retention in Deep Software Standby Mode
■ DMA
 Four fully programmable internal DMA channels
 Two EXDMA channels for external-to-external transfers
 Data Transfer Controller (DTC)
■ Reset and Supply Management
 Power-On Reset (POR) monitor/generator
 Low Voltage Detect (LVD) with precision setting
■ System Clocking with Clock Monitoring
 External crystal, 8 MHz to 14 MHz to Internal PLL
 PLL source to system, USB, and Ethernet
 Internal 125 kHz LOCO for IWDT
 External crystal, 32 kHz for RTC
■ Real Time Clock
 Full calendar function, BCD format
■ Two Independent Watchdog Timers
 125-kHz LOCO operation
■ Up to 14 Communication Interfaces
 USB 2.0 Full-Speed interfaces with PHY (2 ch)
Supports Host/Function/OTG
10 endpoints for types: Control, Interrupt, Bulk, Isochronous
 Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported.
(1 ch)
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY
 CAN ISO11898-1, supports 32 mailboxes (1 ch)
 SCI channels: Asynchronous, clock sync, smartcard, and 9-
bit modes (6 ch)
 I
2
C interfaces up to 1 M bps, SMBus support (2 ch)
 RSPI (2 ch)
■ External Address Space
 Eight CS areas (8 × 16 Mbytes)
 128-Mbyte SDRAM area
 8-/16-/32-bit bus space selectable for each area
■ TFT-LCD up to WQVGA resolution
■ Up to 20 Extended Function Timers
 16-bit MTU2
Input capture, Output Compare, PWM output, phase count
mode (12 ch)
 8-bit TMR (4 ch)
 16-bit CMT (4 ch)
■ 1-MHz ADC units with two combination choices
 12-bit × 8 ch. unit with single sample/hold circuit
 or (2) 10-bit × 4 ch units each with a sample/hold circuit
 AD-converted value addition mode (12-bit A/D converter)
■ 10-bit DAC, 2 channels
■ Up to 128 GPIO
 5 V tolerant, Open-Drain, Internal Pull-up
■ Operation Temp
 –40°C to +85°C
TFLGA85 7 × 7 mm, 0.65 mm pitch
TFLGA145 9 × 9 mm, 0.65 mm pitch
LFBGA176 13 × 13 mm, 0.8 mm pitch
LQFP100 14 × 14 mm, 0. 5mm pitch
LQFP144 20 × 20 mm, 0.5 mm pitch
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash,
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,
RTC, up to 14 communication channels
R01DS0052EJ0140
Rev.1.40
2014.07.16