Datasheet
RX610 Group 5. Electrical Characteristics
R01DS0097EJ0120 Rev.1.20 Page 70 of 84
Feb 20, 2013
5.3.4 Timing of On-Chip Peripheral Modules
Table 5.8 Timing of On-Chip Peripheral Modules (1)
Conditions: V
CC
= PLLV
CC
= AV
CC
= 3.0 to 3.6 V, V
REFH
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= V
REFL
= 0 V, PCLK
= 8 to 50 MHz
T
a
= -20 to +85°C (regular specifications), T
a
= -40 to +85°C (wide-range specifications)
Output load conditions: V
OH
= V
CC
x 0.5, V
OL
= V
CC
x 0.5, I
OH
= -1.0 mA, I
OL
= 1.0 mA, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test
Conditions
I/O ports Output data delay time t
PWD
40 ns Figure 5.14
Input data setup time t
PRS
25 ns
Input data hold time t
PRH
25 ns
TPU Timer output delay time t
TOCD
40 ns Figure 5.15
Timer input setup time t
TICS
25 ns
Timer clock input setup time t
TCKS
25 ns Figure 5.16
Timer clock pulse width
Single-edge
setting
t
TCKWH
1.5 x (1/PCLK) t
cyc
Both-edge setting t
TCKWL
2.5 x (1/PCLK) t
cyc
PPG Pulse output delay time t
POD
40 ns Figure 5.17
8-bit timer Timer output delay time t
TMOD
40 ns Figure 5.18
Timer reset input setup time t
TMRS
25 ns Figure 5.19
Timer clock input setup time t
TMCS
25 ns Figure 5.20
Timer clock pulse width
Single-edge
setting
t
TMCW H
1.5 x (1/PCLK) t
cyc
Both-edge setting t
TMCW L
2.5 x (1/PCLK) t
cyc
WDT Overflow output delay time t
WOVD
40 ns Figure 5.21
SCI Input clock cycle Asynchronous t
Scyc
4 x (1/PCLK) t
cyc
Figure 5.22
Clock
synchronous
6 x (1/PCLK)
Input clock pulse width t
SCKW
0.4 x t
Scyc
0.6 x t
Scyc
t
Scyc
Input clock rise time t
SCKr
20 ns
Input clock fall time t
SCKf
20 ns
Output clock cycle Asynchronous t
Scyc
4 x (1/PCLK) t
cyc
Clock
synchronous
6 x (1/PCLK)
Output clock pulse width t
SCKW
0.4 x t
Scyc
0.6 x t
Scyc
t
Scyc
Output clock rise time t
SCKr
20 ns
Output clock fall time t
SCKf
20 ns
Transmit data delay time t
TXD
40 ns Figure 5.23
Receive data setup time (clock synchronous) t
RXS
40 ns
Receive data hold time (clock synchronous) t
RXH
40 ns
A/D converter Trigger input setup time t
TRGS
25 ns Figure 5.24