Datasheet

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Datasheet

R01DS0097EJ0120 Rev.1.20 Page 1 of 84

Feb 20, 2013

RX610 Group Datasheet

RENESAS 32-Bit MCU

1. Overview

1.1 Features

The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core.

One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with

the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally,

code efficiency is improved by instructions with lengths that are variable in byte units and by an enhanced range of

addressing modes.

Timers, serial communication interfaces, I

C bus interfaces, an A/D converter, and a D/A converter are incorporated as

peripheral functions which are essential to embedded devices.

Facilities for connecting external memory are also included, enabling direct connection to memory and peripheral LSI

circuits. The on-chip memory is flash memory capable of large-capacity, high-speed operation, and this significantly

reduces the cost of configuring systems.

1.1.1 Applications

Office automation equipment and digital industrial equipment

R01DS0097EJ012

Rev.1.2

Feb 20, 2013

Summary of content (86 pages)

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Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU 1. Overview 1.1 Features R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider.
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RX610 Group 1.1.2 1. Overview Outline of Specifications Table 1.1 lists the specifications of the RX610 Group in outline. Table 1.
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RX610 Group 1. Overview Classification Module/Function Description Interrupt Interrupt control unit • Peripheral function interrupts: 116 • External interrupts: 16 (pins IRQ15 to IRQ0) • Non-maskable interrupt: 1 (the NMI pin) • Eight priority orders specifiable External bus extension • The external address space can be divided into eight areas (CS0 to CS7), each of which is independently controllable. Capacity of each area: 16 Mbytes Chip-select signals (CS0# to CS7#) can be output for each area.
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RX610 Group 1.
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RX610 Group 1.2 1. Overview List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product part no. Table 1.2 List of Products Operating Part No. Package ROM Capacity RAM Capacity Data Flash Frequency (Max.
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RX610 Group R 1. Overview 5 F 56 10 8 V N FP Indicates the package. FP: LQFP BG: LFBGA Indicates the characteristic code. N: Regular specifications D: Wide-range specifications Indicates the number of pins. V: 144 pins W: 176 pins Indicates the ROM capacity, RAM capacity, and data flash capacity. 8: 2 Mbytes/128 Kbytes/32 Kbytes 7: 1.5 Mbytes/128 Kbytes/32 Kbytes 6: 1 Mbyte/128 Kbytes/32 Kbytes 4: 768 Kbytes/128 Kbytes/32 Kbytes Indicates the RX610 Group. Indicates the RX600 Series.
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RX610 Group 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram of the RX610 Group.
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RX610 Group 1.4 1. Overview Pin Assignments Figures 1.3 and 1.4 show the pin assignments of the 176-pin LFBGA and the 144-pin LQFP, respectively. Figure 1.5 (assistance diagram) shows the pin assignment the 144-pin LQFP. Tables 1.3 and 1.4 show the lists of pins and pin functions of the 176-pin LFBGA and the 144-pin LQFP, respectively.
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P70/CS3#-B/ADTRG2# P72 P73 P74/ADTRG3# PB1/A9/PO25/TIOCA9/TIOCB9 PB2/A10/PO26/TIOCC9 PB3/A11/PO27/TIOCC9/TIOCD9 PB4/A12/PO28/TIOCA10 PB5/A13/PO29/TIOCA10/TIOCB10 PB6/A14/PO30/TIOCA11 PB7/A15/PO31/TIOCA11/TIOCB11 PC0/A16 PC1/A17 VSS PC2/A18 VCC PC3/A19 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VCC 91 P71/CS4#-C/CS5#-C/CS6#-C/CS7#-C PB0/A8/PO24/TIOCA9 92 89 VSS 93 90 PA6/A6/PO22/TIOCA8 PA5/A5/PO21/TIOCA7/TIOCB7/TCLKG PA2/A2/PO18/TIOCC6/TCLKE 99 PA7/A7/PO23/TIOCA
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1.
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RX610 Group Table 1.3 Pin No. 1.
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RX610 Group Pin No. 1.
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RX610 Group Pin No. 1.
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RX610 Group Pin No. 1.
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RX610 Group Pin No. 1.
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RX610 Group Pin No. 1.
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RX610 Group Table 1.4 1. Overview List of Pins and Pin Functions (144-Pin LQFP) Pin No.
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RX610 Group 1. Overview Pin No.
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RX610 Group 1. Overview Pin No.
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RX610 Group 1. Overview Pin No.
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RX610 Group 1. Overview Pin No.
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RX610 Group 1.5 1. Overview Pin Functions Table 1.5 lists the pin functions. Table 1.5 Pin Functions Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. VCL Input Connect this pin to VSS via a 0.1-µF capacitor. The capacitor should be placed close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). PLLVCC Input Power supply pin for the PLL circuit. Connect it to the system power supply.
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RX610 Group 1. Overview Classifications Pin Name I/O Description Bus control RD# Output Strobe signal which indicates that reading from the external address space is in progress. WR0# Output Strobe signal which indicates that the lower-order byte (D0 to D7) is valid in writing to the external address space, in byte strobe mode. WR1# Output Strobe signal which indicates that the higher-order byte (D8 to D15) is valid in writing to the external address space, in byte strobe mode.
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RX610 Group 1. Overview Classifications Pin Name I/O Description Interrupt NMI Input Non-maskable interrupt request signal IRQ0-A/IRQ0-B Input Maskable request signals I/O Signals for TGRA0 to TGRD0.
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RX610 Group Classifications 16-bit timer pulse unit 1.
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RX610 Group 1. Overview Classifications Pin Name I/O Description Analog power supply AVCC Input Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. AVSS Input Ground pin for the A/D and D/A converters. Connect this pin to the system power supply (0 V). VREFH Input Reference power supply pin for the A/D and D/A converters.
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RX610 Group 2. 2. CPU CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions.
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RX610 Group 2.1 2. CPU General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.
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RX610 Group (8) 2. CPU Floating-Point Status Word (FPSW) The floating-point status word (FPSW) indicates the results of floating-point operations. When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the corresponding Cj flag indicates the source of the exception within the exception handling routine. If the exception handling is masked (Ej = 0), check the Fj flag at the end of a series of processing whether an exception is generated or not.
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RX610 Group 3. Address Space 3. Address Space 3.1 Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figures 3.1 to 3.4 show the memory maps in the respective operating modes of each product. Accessible areas will differ according to the operating mode and states of control bits.
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RX610 Group 3.
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RX610 Group 3.
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RX610 Group 3.
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RX610 Group 3.2 3. Address Space External Address Space The external address space is divided into up to 8 areas, each corresponding to the CSi# signal output from a CSi# (i = 0 to 7) pin. Figure 4.5 shows the address ranges corresponding to the individual CSi# signals (CSi areas, i = 0 to 7) in on-chip ROM disabled external extended mode.
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RX610 Group 4. 4. I/O Registers I/O Registers Table 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 4.
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RX610 Group 5. Electrical Characteristics 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, PLLVCC -0.3 to +4.6 V Input voltage (except for ports 0, 14 to 17) Vin -0.3 to VCC +0.3 V Input voltage (ports 0, 14 to 17*1) Vin -0.3 to +6.5 V Reference power supply voltage VREFH -0.3 to VCC +0.3 V Analog power supply voltage AVCC*2 -0.3 to +4.6 V Analog input voltage VAN -0.3 to VCC +0.
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RX610 Group 5.2 Table 5.2 5. Electrical Characteristics DC Characteristics DC Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Symbol Min. Typ. Max. Unit VIH VCC x 0.8  VCC + 0.3 V VIL -0.3  VCC x 0.2 ΔVT VCC x 0.06   VIH VCC x 0.7  5.8 VIL -0.3  VCC x 0.3 ΔVT VCC x 0.
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RX610 Group 5. Electrical Characteristics Item Symbol Min. Typ. Max. Unit Test Conditions Input pull-up resistor Ports A to E -Ip 10  300 μA VCC = 3.0 to 3.6 V, current Vin = 0 V Input capacitance All input pins Cin   15 pF (except port 0, ports 14 to 17) f = 1 MHz, Port 0, ports 14 to 17 Supply current*3   30   100 Normal*6  35  Increased by BGO  15  Sleep  18 52 All-module-clock-stop mode*8  14 28 Standby Software standby mode  0.08 3.
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RX610 Group Table 5.3 5. Electrical Characteristics Permissible Output Currents Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Permissible output low current (average value per pin) All output pins except Symbol Min. Typ. Max. Unit IOL   2.0 mA IOL   6.0 mA IOL   20.0 mA IOL   4.0 mA IOL   6.0 mA IOL   20.
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RX610 Group 5.3 Table 5.4 5. Electrical Characteristics AC Characteristics Operation Frequency Value Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Unit f 8  100 MHz Operation System clock (ICLK) frequency Peripheral module clock (PCLK) 8  50 External bus clock (BCLK) 8  25 5.3.1 Table 5.
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RX610 Group 5. Electrical Characteristics Oscillator ICLK IRQ IRQMD[1:0] 01 10 SSIER.SSIi SSBY IRQ exception handling IRQMD[1:0] = 10b SSBY = 1 WAIT instruction Figure 5.2 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5.
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RX610 Group 5. Electrical Characteristics EXTAL tDEXT VCC tOSC1 RES# ICLK Figure 5.4 Oscillation Settling Timing tEXH tEXL EXTAL VCC x 0.5 tEXr Figure 5.5 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5.3.2 Table 5.6 5. Electrical Characteristics Control Signal Timing Control Signal Timing Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V ICLK = 8 to 100 MHz, BCLK = 8 to 25 MHz Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Test Item Symbol Min. Max. Unit Conditions 20  tcyc Figure 5.6 1.5  µs tRESW2 * 35  µs NMI pulse width tNMIW 200  ns Figure 5.
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RX610 Group 5.3.3 5. Electrical Characteristics Bus Timing Table 5.7 Bus Timing Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, BCLK = 8 to 25 MHz Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Item Symbol Min. Max. Unit Test Conditions Address delay time tAD  30 ns Figures 5.9 to 5.
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RX610 Group 5. Electrical Characteristics CSRWAIT: 2 CSROFF: 1 RDON: 1 CSON: 0 TW1 TW2 Tend Tn1 Th BCLK Byte write strobe mode tAD tAD tAD tAD A23 to A0 1-write strobe mode A23 to A1 tBCD tBCD tCSD tCSD BC1#, BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tRSD RD# (Read) tRSD tRSS tRSS tRDS tRDH D15 to D0 (Read) Figure 5.9 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5. Electrical Characteristics CSWWAIT: 2 WRON: 1 WDON: 1* CSWOFF: 1 WDOFF: 1* CSON: 0 Tw1 Tw2 Tend Tn1 Th BCLK Byte write strobe mode tAD tAD tAD tAD A23 to A0 1-write strobe mode A23 to A1 tBCD tBCD tCSD tCSD BC1#, BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tWRD tWRS tWRD tWRS WR0#, WR1#, WR# (Write) tWDD tWDH D15 to D0 (Write) Note: * Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.
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RX610 Group 5.
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RX610 Group 5. Electrical Characteristics CSRWAIT: 3 CSWWAIT: 3 TW1 TW2 TW3 (Tend) Tend Tn1 Th BCLK A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait tWTS tWTH tWTS tWTH WAIT# Figure 5.13 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5.3.4 Table 5.8 5. Electrical Characteristics Timing of On-Chip Peripheral Modules Timing of On-Chip Peripheral Modules (1) Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Test Item I/O ports TPU Symbol Min. Max.
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RX610 Group Table 5.8 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (2) Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Test Item 1 2 Symbol Min. * * Max. Unit Conditions Figure 5.
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RX610 Group Table 5.8 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (3) Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Test Item Symbol Min. *1*2 Max. Unit Conditions RIIC SCL input cycle time tSCL 8(10) x (1/PCLK) + 240  ns Figure 5.
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RX610 Group 5. Electrical Characteristics T1 T2 PCLK tPRS tPRH Ports 0 to E (read) (144-pin LQFP) Ports 0 to H (read) (177-pin LFBGA) tPWD Ports 0 to E (write) (144-pin LQFP) Ports 0 to H (write) (177-pin LFBGA) Figure 5.14 I/O Port Input/Output Timing PCLK tTOCD Output compare output* tTICS Input capture input* Notes: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9, TIOCD0, TIOCD3, TIOCD6, TIOCD9 Figure 5.
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RX610 Group 5. Electrical Characteristics PCLK tPOD PO31 to PO0 Figure 5.17 PPG Output Timing PCLK tTMOD TMO0 to TMO3 Figure 5.18 8-Bit Timer Output Timing PCLK tTMRS TMRI0 to TMRI3 Figure 5.19 8-Bit Timer Reset Input Timing PCLK tTMCS tTMCS TMCI0 to TMCI3 tTMCWL Figure 5.20 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5. Electrical Characteristics PCLK tWOVD tWOVD WDTOVF# Figure 5.21 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK6 tScyc Figure 5.22 SCK Clock Input Timing SCK0 to SCK6 tTXD TxD0 to TxD6 (Transmit data) tRXS tRXH RxD0 to RxD6 (Receive data) Figure 5.23 SCI Input/Output Timing: Clock Synchronous Mode PCLK tTRGS ADTRG0# to ADTRG3# Figure 5.24 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5. Electrical Characteristics VIH SDA0, SDA1 VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCL0, SCL1 P* tSf Note: P* Sr* S* tSCLL tSr tSCL tSDAS tSDAH Test conditions VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6V, IOL = 6mA (ICFER.FMPE = 0) VOL = 0.4V, IOL = 15mA (ICFER.FMPE = 1) S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 5.
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RX610 Group 5. Electrical Characteristics TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 5.28 R01DS0097EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group 5.4 5. Electrical Characteristics A/D Conversion Characteristics Table 5.9 A/D Conversion Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz, ADCLK = 4 to 50 MHz Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Min. Resolution 10 Conversion 1 With Typ. Max. Unit 10 10 Bit   μs 3 0.8 (0.3)* When the capacitor is charged 0.
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RX610 Group 5.6 5. Electrical Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.11 ROM (Flash Memory for Code Storage) Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Operating temperature range during programming/erasing: Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Symbol Min. Typ. Max.
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RX610 Group 5.7 5. Electrical Characteristics Data Flash (Flash Memory for Data Storage) Characteristics Table 5.12 Data Flash (Flash Memory for Data Storage) Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Operating temperature range during programming/erasing: Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Symbol Programming time Erasure time Min. Typ. Max.
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RX610 Group 5. Electrical Characteristics Write suspend FCU command Program Suspend tSPD, tDSPD FSTATR0.FRDY Ready Write pulse Ready Not Ready Programming Erasure suspend in suspend priority mode FCU command Erase Suspend Resume Suspend tSESD2, tDSESD2 tSESD1, tDSESD1 FSTATR0.FRDY Ready Erasure pulse Not Ready Ready Erasing Not Ready Erasing Erasure suspend in erasure priority mode FCU command Erase Suspend tSEED, tDSEED FSTATR0.
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RX610 Group Appendix 1. Appendix 1. Package Dimensions Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in "Packages" on Renesas Technology Corp. website. 176-pin LFBGA (PLBG0176GA-A) R01UH0032EJ0120 Feb 20, 2013 Rev.1.
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RX610 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS " *1" AND " *2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION " *3" DOES NOT INCLUDE TRIM OFFSET.
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RX610 Group REVISION HISTORY RX610 Group Datasheet REVISION HISTORY Description Rev. Data Page Summary 0.50 Mar. 24, 2009 − First edition issued 1.00 Apr. 22, 2011 1. Overview 6 Figure 1.2 Block Diagram: Ports F to H added 7 Figure 1.3 Pin Assignment of the 176-pin LFBGA, added 10 to 15 Table 1.3 List of Pins and Pin Functions (176-Pin LFBGA), added Table 1.5 Pin Functions: 21, 25 Description on the BSCANP, PF0 to PF6, PG0 to PG7, and PH0 to PH7 pins added 4.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.