Datasheet

RX610 Group 5. Electrical Characteristics
R01DS0097EJ0120 Rev.1.20 Page 72 of 84
Feb 20, 2013
Table 5.8 Timing of On-Chip Peripheral Modules (3)
Conditions: V
CC
= PLLV
CC
= AV
CC
= 3.0 to 3.6 V, V
REFH
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= V
REFL
= 0 V,
T
a
= -20 to +85°C (regular specifications), T
a
= -40 to +85°C (wide-range specifications)
Item
Symbol
Min. *1*2
Max.
Unit
Test
Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time t
SCL
8(10) x (1/PCLK) + 240 
ns Figure 5.25
SCL input high pulse width t
SCLH
3(5) x (1/PCLK) + 120 
ns
SCL input low pulse width t
SCLL
5 x (1/PCLK) + 120 
ns
SCL, SDA input rising time t
Sr

120
ns
SCL, SDA input falling time t
Sf

120
ns
SCL, SDA
input spike pulse removal
time
t
SP
0 4 x (1/PCLK)
ns
SDA input bus free time t
BUF
5 x (1/PCLK) + 120

ns
Start condition input hold time t
STAH
3(5) x (1/PCLK) + 120

ns
Re-start condition input setup time t
STAS
5 x (1/PCLK) + 120

ns
Stop condition input setup time t
STOS
3(5) x (1/PCLK) + 120

ns
Data input setup time t
SDAS
50

ns
Data input hold time t
SDAH
0

ns
SCL, SDA capacitive load C
b
 550
pF
Boundary scan
(176-pin LFBGA)
TCK clock cycle time tTCKcyc 100  ns
Figure 5.26
TCK clock high level pulse width tTCKH 45  ns
TCK clock low level pulse width tTCKL 45  ns
TCK clock rising time tTCKr

5 ns
TCK clock falling time tTCKf

5 ns
TRST# pulse width tTRSTW 20  Tcyc
Figure 5.27
TMS setup time tTMSS 20

ns
Figure 5.28
TMS hold time tTMSH 20

ns
TDI setup time tTDIS 20

ns
TDI hold time tTDIH 20

ns
TDO data delay time
tTDOD

40
ns
Notes:1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
2. Cb indicates the total capacity of the bus line.