Datasheet

RX610 Group 5. Electrical Characteristics
R01DS0097EJ0120 Rev.1.20 Page 71 of 84
Feb 20, 2013
Table 5.8 Timing of On-Chip Peripheral Modules (2)
Conditions: V
CC
= PLLV
CC
= AV
CC
= 3.0 to 3.6 V, V
REFH
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= V
REFL
= 0 V, PCLK = 8 to 50 MHz
T
a
= -20 to +85°C (regular specifications), T
a
= -40 to +85°C (wide-range specifications)
Item
Symbol
Min. *
1
*
2
Max.
Unit
Test
Conditions
RIIC
(Standard-mode)
ICFER.FMPE = 0
SCL input cycle time t
SCL
8(10) x (1/PCLK) + 1300  ns
Figure 5.25
SCL input high pulse width t
SCLH
3(5) x (1/PCLK) + 300  ns
SCL input low pulse width t
SCLL
5x (1/PCLK) + 1000  ns
SCL, SDA input rising time t
Sr

1000 ns
SCL, SDA input falling time t
Sf

300 ns
SCL, SDA input spike pulse removal
time
t
SP
0 4 x (1/PCLK) ns
SDA input bus free time t
BUF
5x (1/PCLK) + 1000

ns
Start condition input hold time t
STAH
3(5) x (1/PCLK) + 300

ns
Re-start condition input setup time t
STAS
5x (1/PCLK) + 1000

ns
Stop condition input setup time t
STOS
3(5) x (1/PCLK) + 300

ns
Data input setup time t
SDAS
250

ns
Data input hold time t
SDAH
0

ns
SCL, SDA capacitive load
C
b

400
pF
RIIC
(Fast-mode)
ICFER.FMPE = 0
SCL input cycle time t
SCL
8(10) x (1/PCLK) + 600

ns
SCL input high pulse width t
SCLH
3(5) x (1/PCLK) + 300

ns
SCL input low pulse width t
SCLL
5 x (1/PCLK) + 300

ns
SCL, SDA input rising time t
Sr
20 + 0.1C
b
300 ns
SCL, SDA input falling time t
Sf
20 + 0.1C
b
300 ns
SCL, SDA
input spike pulse removal
time
t
SP
0 4 x (1/PCLK) ns
SDA input bus free time t
BUF
5 x (1/PCLK) + 300

ns
Start condition input hold time t
STAH
3(5) x (1/PCLK) + 300

ns
Re-start condition input setup time t
STAS
5 x (1/PCLK) + 300

ns
Stop condition input setup time t
STOS
3(5) x (1/PCLK) + 300

ns
Data input setup time t
SDAS
100

ns
Data input hold time t
SDAH
0

ns
SCL, SDA capacitive load
C
b

400
pF