Datasheet

RX610 Group 5. Electrical Characteristics
R01DS0097EJ0120 Rev.1.20 Page 60 of 84
Feb 20, 2013
5.3 AC Characteristics
Table 5.4 Operation Frequency Value
Conditions: V
CC
= PLLV
CC
= AV
CC
= 3.0 to 3.6 V, V
REFH
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= V
REFL
= 0 V
T
a
= -20 to +85°C (regular specifications), T
a
= -40 to +85°C (wide-range specifications)
Item
Symbol
Min.
Typ.
Max.
Unit
Operation
frequency
System clock (ICLK) f 8  100 MHz
Peripheral module clock (PCLK) 8  50
External bus clock (BCLK) 8  25
5.3.1 Clock Timing
Table 5.5 Clock Timing
Conditions: V
CC
= PLLV
CC
= AV
CC
= 3.0 to 3.6 V, V
REFH
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= V
REFL
= 0 V
ICLK = 8 to 100 MHz, BCLK = 8 to 25 MHz, PCLK = 8 to 50 MHz
T
a
= -20 to +85°C (regular specifications), T
a
= -40 to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test Conditions
Clock cycle time t
cyc
40 125 ns Figure 5.1
Clock high pulse width t
CH
15  ns
Clock low pulse width t
CL
15  ns
Clock rising time t
Cr
 5 ns
Clock falling time t
Cf
 5 ns
Oscillation settling time after reset (crystal) t
OSC1
10  ms Figure 5.4
Oscillation settling time after leaving software
standby mode (crystal)
t
OSC2
10  ms Figure 5.2
Oscillation settling time after leaving deep software
standby mode (crystal)
t
OSC3
10  ms Figure 5.3
External clock output delay settling time t
DEXT
1  ms Figure 5.4
External clock input low pulse width t
EXL
30.71  ns Figure 5.5
External clock input high pulse width t
EXH
30.71  ns
External clock rising time t
EXr
 5 ns
External clock falling time t
EXf
 5 ns
BCLK
t
CH
t
cyc
t
Cf
t
CL
t
Cr
Test conditions V
OH
= V
CC
× 0.7, V
OL
= V
CC
× 0.3, I
OH
= - 1.0mA, I
OL
= 1.0mA, C = 30pF
Figure 5.1 External Bus Clock Timing