Datasheet
R01DS0031EJ0210 Rev.2.10 Page 99 of 111
Jul 31, 2012
M16C/65 Group 5. Electrical Characteristics
V
CC1
= V
CC2
= 3 V
5.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(V
CC1
= V
CC2
= 3 V, V
SS
= 0 V, at T
opr
= -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.1 In No Wait State Setting
Notes:
1. Calculated according to the BCLK frequency as follows:
f
(BCLK)
is 12.5 MHz or less.
2. Calculated according to the BCLK frequency as follows:
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
−CR × ln(1 − V
OL
/V
CC2
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC2
, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t =
−30 pF × 1 kΩ × In(1 − 0.2V
CC2
/V
CC2
)
= 6.7 ns.
Table 5.61 Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol Parameter
Measuring
Condition
Standard
Unit
Min. Max.
t
d(BCLK-AD)
Address output delay time
See
Figure 5.29
30 ns
t
h(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
t
h(RD-AD)
Address output hold time (in relation to RD)
0ns
t
h(WR-AD)
Address output hold time (in relation to WR)
(Note 2) ns
t
d(BCLK-CS)
Chip select output delay time
30 ns
t
h(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
t
d(BCLK-ALE)
ALE signal output delay time
25 ns
t
h(BCLK-ALE)
ALE signal output hold time
−4ns
t
d(BCLK-RD)
RD signal output delay time
30 ns
t
h(BCLK-RD)
RD signal output hold time
0ns
t
d(BCLK-WR)
WR signal output delay time
30 ns
t
h(BCLK-WR)
WR signal output hold time
0ns
t
d(BCLK-DB)
Data output delay time (in relation to BCLK)
40 ns
t
h(BCLK-DB)
Data output hold time (in relation to BCLK)
(3)
0ns
t
d(DB-WR)
Data output delay time (in relation to WR)
(Note 1) ns
t
h(WR-DB)
Data output hold time (in relation to WR)
(3)
(Note 2) ns
0.5 10
9
×
f
BCLK()
----------------------40ns[]–
0.5 10
9
×
f
BCLK()
----------------------10ns[]–
DBi
R
C