Datasheet

R01DS0031EJ0210 Rev.2.10 Page 98 of 111
Jul 31, 2012
M16C/65 Group 5. Electrical Characteristics
Figure 5.28 Timing Diagram
Memory Expansion Mode and Microprocessor Mode
(Effective in wait state setting)
RDY input
RD
BCLK
(Separate bus)
(Multiplexed bus)
RD
(Separate bus)
(Multiplexed bus)
t
su(RDY-BCLK) t
h(BCLK-RDY)
Measuring conditions
y V
= V = 3 V
CC1 CC2
y Input timing voltage: V = 0.6 V, V = 2.4 V
IL IH
y Output timing voltage: V = 1.5 V, V = 1.5 V
OL OH
V = V = 3 V
CC1 CC2
WR, WRL, WRH
WR
, WRL, WRH