Datasheet

R01DS0031EJ0210 Rev.2.10 Page 107 of 111
Jul 31, 2012
M16C/65 Group 5. Electrical Characteristics
Figure 5.33 Timing Diagram
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
BCLK
CSi
ALE
DBi
ADi
BHE
RD
t
cyc
t
d(BCLK-CS)
30ns(max.)
t
d(BCLK-AD)
30ns(max.)
t
d(BCLK-ALE)
25ns(max.) t
h(BCLK-ALE)
-4ns(min.)
t
d(BCLK-RD)
30ns(max.)
Hi-Z
t
su(DB-RD)
Hi-Z
t
d(BCLK-CS)
30ns(max.)
t
d(BCLK-AD)
30ns(max.)
t
d(BCLK-ALE)
25ns(max.)
t
d(BCLK-WR)
30ns(max.)
(0.5 × t -10)ns(min.)
cyc
t
ac4(RD-DB)
(n × t -60)ns(max.)
cyc
V = V = 3V
CC1 CC2
Memory Expansion Mode, Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when accessing external area)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
t
h(BCLK-AD)
0ns(min.)
t
h(BCLK-CS)
0ns(min.)
t
h(RD-AD)
0ns(min.)
t
h(BCLK-RD)
0ns(min.)
t
h(RD-DB)
0ns(min.)
t
h(BCLK-CS)
0ns(min.)
t
h(BCLK-AD)
0ns(min.)
t
h(BCLK-ALE)
-4ns(min.)
t
h(WR-AD)
t
h(BCLK-WR)
0ns(min.)
t
d(DB-WR)
t
h(BCLK-DB)
0ns(min.)
{(n-0.5) × t -40}ns(min.)
cyc
t
h(WR-DB)
(0.5 × t -10)ns(min.)
cyc
Measuring conditions
y V
= V = 3V
CC1 CC2
y Input timing voltage: V = 0.6 V, V = 2.4 V
IL IH
y Output timing voltage: V = 1.5 V, V = 1.5 V
OL OH
t
cyc =
1
f(BCLK)
t
cyc
t
d(BCLK-DB)
40ns(max.)
50ns(min.)